From 22c217b7ba41384ace4165ed9989430d3462801d Mon Sep 17 00:00:00 2001 From: Sathish Kuttan Date: Thu, 31 Jan 2019 14:56:05 -0800 Subject: [PATCH] soc: intel_s1000: Macro to encode multi-level IRQ Add Macro to encode multi-level aggregation of interrupts into an encoded IRQ value Signed-off-by: Sathish Kuttan --- soc/xtensa/intel_s1000/soc.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h index afdda23f988..1ebc100699a 100644 --- a/soc/xtensa/intel_s1000/soc.h +++ b/soc/xtensa/intel_s1000/soc.h @@ -28,6 +28,17 @@ #define INTR_CNTL_IRQ_NUM(_irq) \ (((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1) +/* Macro that aggregates the tri-level interrupt into an IRQ number */ +#define SOC_AGGREGATE_IRQ(ictl_irq, cavs_irq, core_irq) \ + (((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \ + (((cavs_irq) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) | \ + (((ictl_irq) & INTR_CNTL_IRQ_NUM_MASK) << INTR_CNTL_IRQ_NUM_SHIFT)) + +#define CAVS_L2_AGG_INT_LEVEL2 DT_CAVS_ICTL_0_IRQ +#define CAVS_L2_AGG_INT_LEVEL3 DT_CAVS_ICTL_1_IRQ +#define CAVS_L2_AGG_INT_LEVEL4 DT_CAVS_ICTL_2_IRQ +#define CAVS_L2_AGG_INT_LEVEL5 DT_CAVS_ICTL_3_IRQ + #define IOAPIC_EDGE 0 #define IOAPIC_HIGH 0