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soc: renesas: ra: enable wdt support on RA4M1

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Add config to enable wdt after reset reflect wdt Kconfig value

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
This commit is contained in:
The Nguyen 2025-02-25 15:39:43 +07:00 • committed by Benjamin Cabé
commit 22b9a06327
2 changed files with 47 additions and 38 deletions
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1
drivers/watchdog/Kconfig.renesas_ra
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@ -6,6 +6,7 @@ config WDT_RENESAS_RA
default y default y
depends on DT_HAS_RENESAS_RA_WDT_ENABLED depends on DT_HAS_RENESAS_RA_WDT_ENABLED
select HAS_WDT_DISABLE_AT_BOOT select HAS_WDT_DISABLE_AT_BOOT
select SOC_OPTION_SETTING_MEMORY if SOC_SERIES_RA4M1
select USE_RA_FSP_WDT select USE_RA_FSP_WDT
help help
Enable watchdog driver for Renesas RA MCUs Enable watchdog driver for Renesas RA MCUs

44
soc/renesas/ra/ra4m1/soc.c
View file

@ -93,38 +93,47 @@ struct opt_set_mem {
}; };
#ifdef CONFIG_SOC_OPTION_SETTING_MEMORY #ifdef CONFIG_SOC_OPTION_SETTING_MEMORY
const struct opt_set_mem ops __attribute__((section(".rom_registers"))) = { Z_GENERIC_SECTION(".rom_registers")
.ofs0 = { const struct opt_set_mem ops = {
/* /*
* Initial settings for watchdog timers. Set all fields to 1, * Initial settings for watchdog timers. Set all fields to 1,
* disabling watchdog functionality as config options have not * disabling watchdog functionality as config options have not
* yet been implemented. * yet been implemented.
*/ */
.RSVD1 = 0x1, .IWDTSTRT = 0x1, /* Disable independent watchdog timer .ofs0 = {.RSVD1 = 0x1,
*/ .IWDTSTRT = 0x1, /* Disable independent watchdog timer */
.IWDTTOPS = 0x3, .IWDTCKS = 0xf, .IWDTRPES = 0x3, .IWDTRPSS = 0x3, .IWDTTOPS = 0x3,
.IWDTRSTIRQS = 0x1, .RSVD2 = 0x1, .IWDTSTPCTL = 0x1, .RSVD3 = 0x3, .IWDTCKS = 0xf,
.WDTSTRT = 0x1, /* Stop watchdog timer following reset */ .IWDTRPES = 0x3,
.WDTTOPS = 0x3, .WDTCKS = 0xf, .WDTRPES = 0x3, .WDTRPSS = 0x3, .IWDTRPSS = 0x3,
.WDTRSTIRQS = 0x1, .RSVD4 = 0x1, .WDTSTPCTL = 0x1, .RSVD5 = 0x1, .IWDTRSTIRQS = 0x1,
}, .RSVD2 = 0x1,
.ofs1 = { .IWDTSTPCTL = 0x1,
.RSVD1 = 0x3, .RSVD3 = 0x3,
/* Stop watchdog timer following reset */
.WDTSTRT = !IS_ENABLED(CONFIG_WDT_RENESAS_RA_START_IN_BOOT),
.WDTTOPS = 0x3,
.WDTCKS = 0xf,
.WDTRPES = 0x3,
.WDTRPSS = 0x3,
.WDTRSTIRQS = 0x1,
.RSVD4 = 0x1,
.WDTSTPCTL = 0x1,
.RSVD5 = 0x1},
.ofs1 = {.RSVD1 = 0x3,
.LVDAS = 0x1, /* Disable voltage monitor 0 following reset */ .LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
.VDSEL1 = 0x3, .VDSEL1 = 0x3,
.RSVD2 = 0x3, .RSVD2 = 0x3,
.HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay), .HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay),
.RSVD3 = 0x7, .RSVD3 = 0x7,
.HOCOFRQ1 = OFS1_HOCO_FREQ, .HOCOFRQ1 = OFS1_HOCO_FREQ,
.RSVD4 = 0x1ffff, .RSVD4 = 0x1ffff},
},
.mpu = {
/* /*
* Initial settings for MPU. Set all areas to maximum values * Initial settings for MPU. Set all areas to maximum values
* essentially disabling MPU functionality as config options * essentially disabling MPU functionality as config options
* have not yet been implemented. * have not yet been implemented.
*/ */
.SECMPUPCSO = 0x00fffffc, .mpu = {.SECMPUPCSO = 0x00fffffc,
.SECMPUPCEO = 0x00ffffff, .SECMPUPCEO = 0x00ffffff,
.SECMPUPCS1 = 0x00fffffc, .SECMPUPCS1 = 0x00fffffc,
.SECMPUPCE1 = 0x00ffffff, .SECMPUPCE1 = 0x00ffffff,
@ -136,8 +145,7 @@ const struct opt_set_mem ops __attribute__((section(".rom_registers"))) = {
.SECMPUE2 = 0x407fffff, .SECMPUE2 = 0x407fffff,
.SECMPUS3 = 0x40dffffc, .SECMPUS3 = 0x40dffffc,
.SECMPUE3 = 0x40dfffff, .SECMPUE3 = 0x40dfffff,
.SECMPUAC = 0xffffffff, .SECMPUAC = 0xffffffff}};
}};
#endif #endif
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;