ITE drivers/ite_it8xxx2_timer: re-write ite timer driver
Re-write ite timer driver. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
This commit is contained in:
Ruibin Chang
Christopher Friedt
parent
78ef5ace6a
commit
21f0f958fe
4 changed files with 335 additions and 265 deletions
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@ -3,218 +3,103 @@
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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#include <zephyr.h>
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#define DT_DRV_COMPAT ite_it8xxx2_timer
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#include <sys/util.h>
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#include <drivers/timer/system_timer.h>
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#include <drivers/timer/system_timer.h>
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#include <dt-bindings/interrupt-controller/ite-intc.h>
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#include <soc.h>
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#include <soc.h>
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#include <sys/printk.h>
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#include <spinlock.h>
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#include <sys_clock.h>
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/**
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#include <logging/log.h>
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* Macro Define
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LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
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*/
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#define EXT_TIMER_BASE (DT_REG_ADDR_BY_IDX(DT_NODELABEL(timer), 0))
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#define EXT_CTL_B (EXT_TIMER_BASE + 0x10)
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#define EXT_PSC_B (EXT_TIMER_BASE + 0x11)
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#define EXT_LLR_B (EXT_TIMER_BASE + 0x14)
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#define EXT_LHR_B (EXT_TIMER_BASE + 0x15)
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#define EXT_LH2R_B (EXT_TIMER_BASE + 0x16)
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#define EXT_LH3R_B (EXT_TIMER_BASE + 0x17)
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#define EXT_CNTO_B (EXT_TIMER_BASE + 0x48)
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#define CTIMER_HW_TIMER_INDEX EXT_TIMER_3
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/* Control external timer3~8 */
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#define ETIMER_HW_TIMER_INDEX EXT_TIMER_5
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#define IT8XXX2_EXT_TIMER_BASE (DT_INST_REG_ADDR(0))/*0x00F01F10*/
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#define RTIMER_HW_TIMER_INDEX EXT_TIMER_7
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#define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
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#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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#define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \
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#define MAX_TICKS ((0x00ffffffu - CYC_PER_TICK) / CYC_PER_TICK)
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(n << 3))
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#define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \
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(n << 2))
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#define MAX_TIMER_NUM 8
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/* Event timer configurations */
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#define REG_ADDR_OFFSET(idx) (idx * MAX_TIMER_NUM)
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#define EVENT_TIMER EXT_TIMER_3
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#define IDX_SHIFT(idx, rsh, lsh) ((idx >> rsh) << lsh)
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#define EVENT_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 0, irq)
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#define EVENT_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 0, flags)
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/* Event timer max count is 512 sec (base on clock source 32768Hz) */
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#define EVENT_TIMER_MAX_CNT 0x00FFFFFFUL
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enum _EXT_TIMER_PRESCALE_TYPE_ {
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/* Free run timer configurations */
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ET_PSR_32K,
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#define FREE_RUN_TIMER EXT_TIMER_4
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ET_PSR_1K,
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#define FREE_RUN_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 1, irq)
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ET_PSR_32,
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#define FREE_RUN_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 1, flags)
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ET_PSR_8M,
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/* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
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};
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#define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL
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enum _EXT_TIMER_IDX_ {
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EXT_TIMER_3 = 0, /* ctimer */
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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EXT_TIMER_4, /* ctimer */
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/*
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EXT_TIMER_5, /* etimer */
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* One shot timer configurations
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EXT_TIMER_6, /* NULL */
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*
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EXT_TIMER_7, /* rtimer */
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* NOTE: Timer1/2 register address isn't regular like timer3/4/5/6/7/8, and
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EXT_TIMER_8 /* NULL */
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* timer1 is used for printing watchdog warning message. So now we use
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};
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* timer2 only one shot to wake up chip and change pll.
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*/
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/* Be careful of overflow issue */
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#define WDT_BASE DT_REG_ADDR(DT_NODELABEL(twd0))
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#define MILLI_SEC_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
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#define WDT_REG (struct wdt_it8xxx2_regs *)(WDT_BASE)
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#define MICRO_SEC_TO_COUNT(hz, us) ((hz) * (us) / 1000000)
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#define ONE_SHOT_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, irq)
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#define ONE_SHOT_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, flags)
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/**
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#endif
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* ITE timer control api
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*/
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#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
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static void ite_timer_reload(uint8_t idx, uint32_t cnt)
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/*
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{
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* One system (kernel) tick is as how much HW timer counts
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/* timer_start */
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*
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sys_set_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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* NOTE: Event and free run timer individually select the same clock source
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sys_write8(((cnt >> 24) & 0xFF), (EXT_LH3R_B + REG_ADDR_OFFSET(idx)));
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* frequency, so they can use the same HW_CNT_PER_SYS_TICK to tranform
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sys_write8(((cnt >> 16) & 0xFF), (EXT_LH2R_B + REG_ADDR_OFFSET(idx)));
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* unit between HW count and system tick. If clock source frequency is
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sys_write8(((cnt >> 8) & 0xFF), (EXT_LHR_B + REG_ADDR_OFFSET(idx)));
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* different, then we should define another to tranform.
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sys_write8(((cnt >> 0) & 0xFF), (EXT_LLR_B + REG_ADDR_OFFSET(idx)));
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*/
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}
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#define HW_CNT_PER_SYS_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* The following function:
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/* Event timer max count is as how much system (kernal) tick */
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* disable, enable, check_flag, clear_flag, wait,
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#define EVEN_TIMER_MAX_CNT_SYS_TICK (EVENT_TIMER_MAX_CNT \
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* can be used only for Timer #3 ~ #7
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/ HW_CNT_PER_SYS_TICK)
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*/
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static void ite_timer_disable(uint8_t idx)
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enum ext_clk_src_sel {
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{
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EXT_PSR_32P768K = 0,
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CLEAR_MASK(IER19, (BIT(3 + (idx))));
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EXT_PSR_1P024K,
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}
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EXT_PSR_32,
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EXT_PSR_8M,
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static void ite_timer_enable(uint8_t idx)
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};
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{
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SET_MASK(IER19, (BIT(3 + (idx))));
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/*
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}
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* 24-bit timers: external timer 3, 5, and 7
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* 32-bit timers: external timer 4, 6, and 8
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static void ite_timer_clear_flag(uint8_t idx)
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*/
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{
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enum ext_timer_idx {
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ISR19 = BIT(3 + (idx));
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EXT_TIMER_3 = 0, /* Event timer */
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}
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EXT_TIMER_4, /* Free run timer */
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EXT_TIMER_5,
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/**
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EXT_TIMER_6,
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* timer_init()
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EXT_TIMER_7,
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*/
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EXT_TIMER_8,
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static int timer_init(uint8_t idx, uint8_t psr, uint8_t initial_state,
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};
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uint8_t enable_isr, uint32_t cnt)
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{
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static struct k_spinlock lock;
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/* Setup Triggered Mode -> Rising-Edge Trig. */
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/* Last HW count that we called sys_clock_announce() */
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if (idx != EXT_TIMER_8) {
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static volatile uint32_t last_announced_hw_cnt;
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IELMR19 |= BIT(3 + idx);
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IPOLR19 &= (~(BIT(3 + idx)));
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} else {
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IELMR10 |= BIT(0);
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IPOLR10 &= (~(BIT(0)));
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}
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/* Setup prescaler */
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sys_write8(psr, (EXT_PSC_B + REG_ADDR_OFFSET(idx)));
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/* Reload counter */
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ite_timer_reload(idx, cnt);
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/* Start counting or not */
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if (initial_state) {
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/* timer restart */
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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/* timer_start */
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sys_set_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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} else {
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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}
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/* Enable ISR or not & Clear flag */
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if (idx != EXT_TIMER_8) {
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if (enable_isr) {
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ite_timer_enable(idx);
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} else {
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ite_timer_disable(idx);
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}
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ite_timer_clear_flag(idx);
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} else {
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if (enable_isr) {
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SET_MASK(IER10, BIT(0));
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} else {
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CLEAR_MASK(IER10, BIT(0));
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}
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ISR10 = BIT(0);
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}
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return 0;
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}
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static int timer_init_ms(uint8_t idx, uint8_t psr, uint8_t initial_state,
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uint8_t enable_isr, uint32_t u32MilliSec)
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{
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uint32_t cnt;
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if (psr == ET_PSR_32K) {
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cnt = MILLI_SEC_TO_COUNT(32768, u32MilliSec);
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} else if (psr == ET_PSR_1K) {
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cnt = MILLI_SEC_TO_COUNT(1024, u32MilliSec);
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} else if (psr == ET_PSR_32) {
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cnt = MILLI_SEC_TO_COUNT(32, u32MilliSec);
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} else if (psr == ET_PSR_8M) {
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cnt = u32MilliSec * 8000; /* fixed overflow issue */
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} else {
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return -1;
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}
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/* 24-bits only */
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if (cnt >> 24) {
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return -2;
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}
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return timer_init(idx, psr, initial_state, enable_isr, cnt);
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}
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static void timer_init_combine(uint8_t idx, uint8_t bEnable)
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{
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if (bEnable) {
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sys_set_bit((EXT_CTL_B + IDX_SHIFT(idx, 1, (1 + 3))), 3);
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} else {
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sys_clear_bit((EXT_CTL_B + IDX_SHIFT(idx, 1, (1 + 3))), 3);
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}
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}
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static uint32_t get_timer_combine_count(uint8_t idx)
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{
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return sys_read32(EXT_CNTO_B + ((IDX_SHIFT(idx, 1, 1) + 1) * 4));
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}
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static void timer_count_reset(uint8_t idx, uint32_t cnt)
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{
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/* Reload counter */
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ite_timer_reload(idx, cnt);
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/* Start counting or not */
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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/* timer_start */
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sys_set_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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}
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static struct k_spinlock lock;
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static volatile uint32_t accumulated_cycle_count;
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static void timer_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + ((ETIMER_HW_TIMER_INDEX) * MAX_TIMER_NUM)),
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0);
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uint32_t dticks = (get_timer_combine_count(CTIMER_HW_TIMER_INDEX)
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- accumulated_cycle_count) / CYC_PER_TICK;
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accumulated_cycle_count += dticks * CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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sys_clock_announce(dticks);
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}
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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#define TIMER_CHANGE_PLL EXT_TIMER_8
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static void timer_5ms_one_shot_isr(const void *unused)
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static void timer_5ms_one_shot_isr(const void *unused)
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{
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{
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ARG_UNUSED(unused);
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ARG_UNUSED(unused);
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/*
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/*
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* We are here because we have completed changing PLL sequence.
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* We are here because we have completed changing PLL sequence,
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* Disabled the timer.
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* so disabled one shot timer interrupt.
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*/
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*/
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timer_init_ms(TIMER_CHANGE_PLL, ET_PSR_32K, 0, 0, 5);
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irq_disable(ONE_SHOT_TIMER_IRQ);
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}
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}
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/*
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/*
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@ -223,52 +108,258 @@ static void timer_5ms_one_shot_isr(const void *unused)
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*/
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*/
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void timer_5ms_one_shot(void)
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void timer_5ms_one_shot(void)
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{
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{
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/* Initialize interrupt handler of external timer8. */
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struct wdt_it8xxx2_regs *const timer2_reg = WDT_REG;
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IRQ_CONNECT(DT_IRQ_BY_IDX(DT_NODELABEL(timer), 8, irq),
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uint32_t hw_cnt;
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0, timer_5ms_one_shot_isr, NULL,
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DT_IRQ_BY_IDX(DT_NODELABEL(timer), 8, flags));
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/* Initialize interrupt handler of one shot timer */
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/* enable 5ms timer with 32.768khz clock source */
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IRQ_CONNECT(ONE_SHOT_TIMER_IRQ, 0, timer_5ms_one_shot_isr, NULL,
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timer_init_ms(TIMER_CHANGE_PLL, ET_PSR_32K, 1, 1, 5);
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ONE_SHOT_TIMER_FLAG);
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/* Set rising edge triggered of one shot timer */
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ite_intc_irq_priority_set(ONE_SHOT_TIMER_IRQ, 0, ONE_SHOT_TIMER_FLAG);
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/* Clear interrupt status of one shot timer */
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ite_intc_isr_clear(ONE_SHOT_TIMER_IRQ);
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/* Set clock source of one shot timer */
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timer2_reg->ET2PSR = EXT_PSR_32P768K;
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/*
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* Set count of one shot timer,
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* and after write ET2CNTLLR timer will start
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*/
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hw_cnt = MS_TO_COUNT(32768, 5/*ms*/);
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timer2_reg->ET2CNTLH2R = (uint8_t)((hw_cnt >> 16) & 0xff);
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timer2_reg->ET2CNTLHR = (uint8_t)((hw_cnt >> 8) & 0xff);
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timer2_reg->ET2CNTLLR = (uint8_t)(hw_cnt & 0xff);
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irq_enable(ONE_SHOT_TIMER_IRQ);
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}
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}
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#endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
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#endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
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int sys_clock_driver_init(const struct device *dev)
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static void evt_timer_isr(const void *unused)
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{
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{
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timer_init_combine(CTIMER_HW_TIMER_INDEX, TRUE);
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ARG_UNUSED(unused);
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timer_init(CTIMER_HW_TIMER_INDEX, ET_PSR_32K, TRUE, FALSE, 0);
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irq_connect_dynamic(DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq),
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/* Disable event timer */
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0, timer_isr, NULL,
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) &= ~IT8XXX2_EXT_ETXEN;
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DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, flags));
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/* W/C event timer interrupt status */
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timer_init_ms(ETIMER_HW_TIMER_INDEX, ET_PSR_32K, FALSE, TRUE, 0);
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ite_intc_isr_clear(EVENT_TIMER_IRQ);
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return 0;
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/*
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* Get free run observer count from last time announced and
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* trnaform unit to system tick
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*/
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uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
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last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
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last_announced_hw_cnt += (dticks * HW_CNT_PER_SYS_TICK);
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sys_clock_announce(dticks);
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} else {
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/* Enable and re-start event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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/* Informs kernel that one system tick has elapsed */
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||||||
|
sys_clock_announce(1);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void sys_clock_set_timeout(int32_t ticks, bool idle)
|
void sys_clock_set_timeout(int32_t ticks, bool idle)
|
||||||
{
|
{
|
||||||
|
uint32_t hw_cnt;
|
||||||
|
|
||||||
ARG_UNUSED(idle);
|
ARG_UNUSED(idle);
|
||||||
|
|
||||||
|
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
|
||||||
|
/* Always return for non-tickless kernel system */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Critical section */
|
||||||
k_spinlock_key_t key = k_spin_lock(&lock);
|
k_spinlock_key_t key = k_spin_lock(&lock);
|
||||||
|
|
||||||
ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
|
/* NOTE: To reduce cpu effort, we don't add critical section here */
|
||||||
ticks = MAX(MIN(ticks, (int32_t)MAX_TICKS), 1);
|
if (ticks == K_TICKS_FOREVER) {
|
||||||
timer_count_reset(ETIMER_HW_TIMER_INDEX, ticks * CYC_PER_TICK);
|
hw_cnt = EVENT_TIMER_MAX_CNT;
|
||||||
|
} else if (ticks <= 1) {
|
||||||
|
/*
|
||||||
|
* Ticks <= 1 means the kernel wants the tick announced
|
||||||
|
* as soon as possible, ideally no more than one system tick
|
||||||
|
* in the future. So set event timer count to 1 system tick or
|
||||||
|
* at least 1 hw count.
|
||||||
|
*/
|
||||||
|
hw_cnt = MAX((1 * HW_CNT_PER_SYS_TICK), 1);
|
||||||
|
} else {
|
||||||
|
if (ticks > EVEN_TIMER_MAX_CNT_SYS_TICK)
|
||||||
|
/*
|
||||||
|
* Set event timer count to EVENT_TIMER_MAX_CNT, after
|
||||||
|
* interrupt fired the remaining time will be set again
|
||||||
|
* by sys_clock_announce().
|
||||||
|
*/
|
||||||
|
hw_cnt = EVENT_TIMER_MAX_CNT;
|
||||||
|
else
|
||||||
|
/*
|
||||||
|
* Set event timer count to system tick or at least
|
||||||
|
* 1 hw count
|
||||||
|
*/
|
||||||
|
hw_cnt = MAX((ticks * HW_CNT_PER_SYS_TICK), 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set event timer 24-bit count */
|
||||||
|
IT8XXX2_EXT_CNTX(EVENT_TIMER) = hw_cnt;
|
||||||
|
|
||||||
|
/* Enable and re-start event timer */
|
||||||
|
IT8XXX2_EXT_CTRLX(EVENT_TIMER) |= (IT8XXX2_EXT_ETXEN |
|
||||||
|
IT8XXX2_EXT_ETXRST);
|
||||||
|
|
||||||
|
/* W/C event timer interrupt status */
|
||||||
|
ite_intc_isr_clear(EVENT_TIMER_IRQ);
|
||||||
|
|
||||||
k_spin_unlock(&lock, key);
|
k_spin_unlock(&lock, key);
|
||||||
|
|
||||||
|
LOG_DBG("timeout is 0x%x, set hw count 0x%x", ticks, hw_cnt);
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t sys_clock_elapsed(void)
|
uint32_t sys_clock_elapsed(void)
|
||||||
{
|
{
|
||||||
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
|
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
|
||||||
|
/* Always return 0 for non-tickless kernel system */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
k_spinlock_key_t key = k_spin_lock(&lock);
|
|
||||||
|
|
||||||
uint32_t ret = (get_timer_combine_count(CTIMER_HW_TIMER_INDEX)
|
/* Critical section */
|
||||||
- accumulated_cycle_count) / CYC_PER_TICK;
|
k_spinlock_key_t key = k_spin_lock(&lock);
|
||||||
|
/*
|
||||||
|
* Get free run observer count from last time announced and trnaform
|
||||||
|
* unit to system tick
|
||||||
|
*/
|
||||||
|
uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
|
||||||
|
last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
|
||||||
k_spin_unlock(&lock, key);
|
k_spin_unlock(&lock, key);
|
||||||
return ret;
|
|
||||||
|
return dticks;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t sys_clock_cycle_get_32(void)
|
uint32_t sys_clock_cycle_get_32(void)
|
||||||
{
|
{
|
||||||
return get_timer_combine_count(CTIMER_HW_TIMER_INDEX);
|
/*
|
||||||
|
* Get free run observer count and trnaform unit to system tick
|
||||||
|
*
|
||||||
|
* NOTE: Timer is counting down from 0xffffffff. In not combined
|
||||||
|
* mode, the observer count value is the same as count, so after
|
||||||
|
* NOT count operation we can get counting up value; In
|
||||||
|
* combined mode, the observer count value is the same as NOT
|
||||||
|
* count operation.
|
||||||
|
*/
|
||||||
|
uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)))
|
||||||
|
/ HW_CNT_PER_SYS_TICK;
|
||||||
|
|
||||||
|
return dticks;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int timer_init(enum ext_timer_idx ext_timer,
|
||||||
|
enum ext_clk_src_sel clock_source_sel,
|
||||||
|
uint32_t raw,
|
||||||
|
uint32_t ms,
|
||||||
|
uint8_t first_time_enable,
|
||||||
|
uint32_t irq_num,
|
||||||
|
uint32_t irq_flag,
|
||||||
|
uint8_t with_int,
|
||||||
|
uint8_t start)
|
||||||
|
{
|
||||||
|
uint32_t hw_cnt;
|
||||||
|
|
||||||
|
if (raw) {
|
||||||
|
hw_cnt = ms;
|
||||||
|
} else {
|
||||||
|
if (clock_source_sel == EXT_PSR_32P768K)
|
||||||
|
hw_cnt = MS_TO_COUNT(32768, ms);
|
||||||
|
else if (clock_source_sel == EXT_PSR_1P024K)
|
||||||
|
hw_cnt = MS_TO_COUNT(1024, ms);
|
||||||
|
else if (clock_source_sel == EXT_PSR_32)
|
||||||
|
hw_cnt = MS_TO_COUNT(32, ms);
|
||||||
|
else if (clock_source_sel == EXT_PSR_8M)
|
||||||
|
hw_cnt = 8000 * ms;
|
||||||
|
else {
|
||||||
|
LOG_ERR("Timer %d clock source error !", ext_timer);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (hw_cnt == 0) {
|
||||||
|
LOG_ERR("Timer %d count shouldn't be 0 !", ext_timer);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (first_time_enable) {
|
||||||
|
/* Enable and re-start external timer x */
|
||||||
|
IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
|
||||||
|
IT8XXX2_EXT_ETXRST);
|
||||||
|
/* Disable external timer x */
|
||||||
|
IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set rising edge triggered of external timer x */
|
||||||
|
ite_intc_irq_priority_set(irq_num, 0, irq_flag);
|
||||||
|
|
||||||
|
/* Clear interrupt status of external timer x */
|
||||||
|
ite_intc_isr_clear(irq_num);
|
||||||
|
|
||||||
|
/* Set clock source of external timer x */
|
||||||
|
IT8XXX2_EXT_PSRX(ext_timer) = clock_source_sel;
|
||||||
|
|
||||||
|
/* Set count of external timer x */
|
||||||
|
IT8XXX2_EXT_CNTX(ext_timer) = hw_cnt;
|
||||||
|
|
||||||
|
/* Disable external timer x */
|
||||||
|
IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
|
||||||
|
if (start)
|
||||||
|
/* Enable and re-start external timer x */
|
||||||
|
IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
|
||||||
|
IT8XXX2_EXT_ETXRST);
|
||||||
|
|
||||||
|
if (with_int)
|
||||||
|
irq_enable(irq_num);
|
||||||
|
else
|
||||||
|
irq_disable(irq_num);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int sys_clock_driver_init(const struct device *dev)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ARG_UNUSED(dev);
|
||||||
|
|
||||||
|
/* Set 32-bit timer4 for free run*/
|
||||||
|
ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, TRUE,
|
||||||
|
FREE_RUN_TIMER_MAX_CNT, TRUE, FREE_RUN_TIMER_IRQ,
|
||||||
|
FREE_RUN_TIMER_FLAG, FALSE, TRUE);
|
||||||
|
if (ret < 0) {
|
||||||
|
LOG_ERR("Init free run timer failed");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set 24-bit timer3 for timeout event */
|
||||||
|
IRQ_CONNECT(EVENT_TIMER_IRQ, 0, evt_timer_isr, NULL, EVENT_TIMER_FLAG);
|
||||||
|
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
|
||||||
|
ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, TRUE,
|
||||||
|
EVENT_TIMER_MAX_CNT, TRUE, EVENT_TIMER_IRQ,
|
||||||
|
EVENT_TIMER_FLAG, TRUE, FALSE);
|
||||||
|
} else {
|
||||||
|
/* Start a event timer in one system tick */
|
||||||
|
ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, TRUE,
|
||||||
|
MAX((1 * HW_CNT_PER_SYS_TICK), 1), TRUE,
|
||||||
|
EVENT_TIMER_IRQ, EVENT_TIMER_FLAG,
|
||||||
|
TRUE, TRUE);
|
||||||
|
}
|
||||||
|
if (ret < 0) {
|
||||||
|
LOG_ERR("Init event timer failed");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -263,23 +263,21 @@
|
||||||
compatible = "ite,it8xxx2-watchdog";
|
compatible = "ite,it8xxx2-watchdog";
|
||||||
reg = <0x00f01f00 0x0062>;
|
reg = <0x00f01f00 0x0062>;
|
||||||
label = "TWD_0";
|
label = "TWD_0";
|
||||||
interrupts = <30 IRQ_TYPE_EDGE_RISING>;
|
interrupts = <IT8XXX2_IRQ_TIMER1 IRQ_TYPE_EDGE_RISING /* Warning timer */
|
||||||
|
IT8XXX2_IRQ_TIMER2 IRQ_TYPE_EDGE_RISING>; /* One shot timer */
|
||||||
interrupt-parent = <&intc>;
|
interrupt-parent = <&intc>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer: timer@f01f10 {
|
timer: timer@f01f10 {
|
||||||
compatible = "ite,it8xxx2-timer";
|
compatible = "ite,it8xxx2-timer";
|
||||||
reg = <0x00f01f00 0x0062>;
|
reg = <0x00f01f10 0x0052>;
|
||||||
label = "sys_clock";
|
label = "TIMER";
|
||||||
interrupts = <0 IRQ_TYPE_NONE
|
interrupts = <IT8XXX2_IRQ_TIMER3 IRQ_TYPE_EDGE_RISING /* Event timer */
|
||||||
30 IRQ_TYPE_EDGE_RISING
|
IT8XXX2_IRQ_TIMER4 IRQ_TYPE_EDGE_RISING /* Free run timer */
|
||||||
58 IRQ_TYPE_EDGE_RISING
|
IT8XXX2_IRQ_TIMER5 IRQ_TYPE_EDGE_RISING
|
||||||
155 IRQ_TYPE_EDGE_FALLING
|
IT8XXX2_IRQ_TIMER6 IRQ_TYPE_EDGE_RISING
|
||||||
156 IRQ_TYPE_EDGE_FALLING
|
IT8XXX2_IRQ_TIMER7 IRQ_TYPE_EDGE_RISING
|
||||||
157 IRQ_TYPE_EDGE_FALLING
|
IT8XXX2_IRQ_TIMER8 IRQ_TYPE_EDGE_RISING>;
|
||||||
158 IRQ_TYPE_EDGE_FALLING
|
|
||||||
159 IRQ_TYPE_EDGE_FALLING
|
|
||||||
80 IRQ_TYPE_EDGE_RISING>;
|
|
||||||
interrupt-parent = <&intc>;
|
interrupt-parent = <&intc>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -24,6 +24,7 @@
|
||||||
#define IT8XXX2_IRQ_WU24 17
|
#define IT8XXX2_IRQ_WU24 17
|
||||||
#define IT8XXX2_IRQ_WU22 21
|
#define IT8XXX2_IRQ_WU22 21
|
||||||
/* Group 3 */
|
/* Group 3 */
|
||||||
|
#define IT8XXX2_IRQ_TIMER1 30
|
||||||
#define IT8XXX2_IRQ_WU21 31
|
#define IT8XXX2_IRQ_WU21 31
|
||||||
/* Group 5 */
|
/* Group 5 */
|
||||||
#define IT8XXX2_IRQ_WU50 40
|
#define IT8XXX2_IRQ_WU50 40
|
||||||
|
|
@ -43,6 +44,8 @@
|
||||||
#define IT8XXX2_IRQ_WU65 53
|
#define IT8XXX2_IRQ_WU65 53
|
||||||
#define IT8XXX2_IRQ_WU66 54
|
#define IT8XXX2_IRQ_WU66 54
|
||||||
#define IT8XXX2_IRQ_WU67 55
|
#define IT8XXX2_IRQ_WU67 55
|
||||||
|
/* Group 7 */
|
||||||
|
#define IT8XXX2_IRQ_TIMER2 58
|
||||||
/* Group 9 */
|
/* Group 9 */
|
||||||
#define IT8XXX2_IRQ_WU70 72
|
#define IT8XXX2_IRQ_WU70 72
|
||||||
#define IT8XXX2_IRQ_WU71 73
|
#define IT8XXX2_IRQ_WU71 73
|
||||||
|
|
@ -53,6 +56,7 @@
|
||||||
#define IT8XXX2_IRQ_WU76 78
|
#define IT8XXX2_IRQ_WU76 78
|
||||||
#define IT8XXX2_IRQ_WU77 79
|
#define IT8XXX2_IRQ_WU77 79
|
||||||
/* Group 10 */
|
/* Group 10 */
|
||||||
|
#define IT8XXX2_IRQ_TIMER8 80
|
||||||
#define IT8XXX2_IRQ_WU88 85
|
#define IT8XXX2_IRQ_WU88 85
|
||||||
#define IT8XXX2_IRQ_WU89 86
|
#define IT8XXX2_IRQ_WU89 86
|
||||||
#define IT8XXX2_IRQ_WU90 87
|
#define IT8XXX2_IRQ_WU90 87
|
||||||
|
|
@ -124,6 +128,12 @@
|
||||||
#define IT8XXX2_IRQ_WU124 145
|
#define IT8XXX2_IRQ_WU124 145
|
||||||
#define IT8XXX2_IRQ_WU125 146
|
#define IT8XXX2_IRQ_WU125 146
|
||||||
#define IT8XXX2_IRQ_WU126 147
|
#define IT8XXX2_IRQ_WU126 147
|
||||||
|
/* Group 19 */
|
||||||
|
#define IT8XXX2_IRQ_TIMER3 155
|
||||||
|
#define IT8XXX2_IRQ_TIMER4 156
|
||||||
|
#define IT8XXX2_IRQ_TIMER5 157
|
||||||
|
#define IT8XXX2_IRQ_TIMER6 158
|
||||||
|
#define IT8XXX2_IRQ_TIMER7 159
|
||||||
/* Group 20 */
|
/* Group 20 */
|
||||||
#define IT8XXX2_IRQ_USBPD0 165
|
#define IT8XXX2_IRQ_USBPD0 165
|
||||||
#define IT8XXX2_IRQ_USBPD1 166
|
#define IT8XXX2_IRQ_USBPD1 166
|
||||||
|
|
|
||||||
|
|
@ -1200,39 +1200,10 @@ struct wdt_it8xxx2_regs {
|
||||||
#define IT8XXX2_WDT_ET1TC BIT(1)
|
#define IT8XXX2_WDT_ET1TC BIT(1)
|
||||||
#define IT8XXX2_WDT_ET1RST BIT(0)
|
#define IT8XXX2_WDT_ET1RST BIT(0)
|
||||||
|
|
||||||
#define ET3CTRL ECREG(EC_REG_BASE_ADDR + 0x1F10)
|
/* External Timer register fields */
|
||||||
#define ET3PSR ECREG(EC_REG_BASE_ADDR + 0x1F11)
|
/* External Timer 3~8 control */
|
||||||
#define ET3CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F14)
|
#define IT8XXX2_EXT_ETXRST BIT(1)
|
||||||
#define ET3CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F15)
|
#define IT8XXX2_EXT_ETXEN BIT(0)
|
||||||
#define ET3CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F16)
|
|
||||||
#define ET4CTRL ECREG(EC_REG_BASE_ADDR + 0x1F18)
|
|
||||||
#define ET4PSR ECREG(EC_REG_BASE_ADDR + 0x1F19)
|
|
||||||
#define ET4CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F1C)
|
|
||||||
#define ET4CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F1D)
|
|
||||||
#define ET4CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F1E)
|
|
||||||
#define ET4CNTLH3R ECREG(EC_REG_BASE_ADDR + 0x1F1F)
|
|
||||||
#define ET5CTRL ECREG(EC_REG_BASE_ADDR + 0x1F20)
|
|
||||||
#define ET5PSR ECREG(EC_REG_BASE_ADDR + 0x1F21)
|
|
||||||
#define ET5CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F24)
|
|
||||||
#define ET5CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F25)
|
|
||||||
#define ET5CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F26)
|
|
||||||
#define ET6CTRL ECREG(EC_REG_BASE_ADDR + 0x1F28)
|
|
||||||
#define ET6PSR ECREG(EC_REG_BASE_ADDR + 0x1F29)
|
|
||||||
#define ET6CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F2C)
|
|
||||||
#define ET6CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F2D)
|
|
||||||
#define ET6CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F2E)
|
|
||||||
#define ET6CNTLH3R ECREG(EC_REG_BASE_ADDR + 0x1F2F)
|
|
||||||
#define ET7CTRL ECREG(EC_REG_BASE_ADDR + 0x1F30)
|
|
||||||
#define ET7PSR ECREG(EC_REG_BASE_ADDR + 0x1F31)
|
|
||||||
#define ET7CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F34)
|
|
||||||
#define ET7CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F35)
|
|
||||||
#define ET7CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F36)
|
|
||||||
#define ET8CTRL ECREG(EC_REG_BASE_ADDR + 0x1F38)
|
|
||||||
#define ET8PSR ECREG(EC_REG_BASE_ADDR + 0x1F39)
|
|
||||||
#define ET8CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F3C)
|
|
||||||
#define ET8CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F3D)
|
|
||||||
#define ET8CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F3E)
|
|
||||||
#define ET8CNTLH3R ECREG(EC_REG_BASE_ADDR + 0x1F3F)
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
*
|
*
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue