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ITE drivers/ite_it8xxx2_timer: re-write ite timer driver

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Re-write ite timer driver.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
This commit is contained in:
Ruibin Chang 2021-04-22 18:18:52 +08:00 • committed by Christopher Friedt
commit 21f0f958fe
4 changed files with 335 additions and 265 deletions
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37
soc/riscv/riscv-ite/common/chip_chipregs.h
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@ -1200,39 +1200,10 @@ struct wdt_it8xxx2_regs {
#define IT8XXX2_WDT_ET1TC BIT(1)
#define IT8XXX2_WDT_ET1RST BIT(0)
#define ET3CTRL ECREG(EC_REG_BASE_ADDR + 0x1F10)
#define ET3PSR ECREG(EC_REG_BASE_ADDR + 0x1F11)
#define ET3CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F14)
#define ET3CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F15)
#define ET3CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F16)
#define ET4CTRL ECREG(EC_REG_BASE_ADDR + 0x1F18)
#define ET4PSR ECREG(EC_REG_BASE_ADDR + 0x1F19)
#define ET4CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F1C)
#define ET4CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F1D)
#define ET4CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F1E)
#define ET4CNTLH3R ECREG(EC_REG_BASE_ADDR + 0x1F1F)
#define ET5CTRL ECREG(EC_REG_BASE_ADDR + 0x1F20)
#define ET5PSR ECREG(EC_REG_BASE_ADDR + 0x1F21)
#define ET5CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F24)
#define ET5CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F25)
#define ET5CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F26)
#define ET6CTRL ECREG(EC_REG_BASE_ADDR + 0x1F28)
#define ET6PSR ECREG(EC_REG_BASE_ADDR + 0x1F29)
#define ET6CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F2C)
#define ET6CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F2D)
#define ET6CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F2E)
#define ET6CNTLH3R ECREG(EC_REG_BASE_ADDR + 0x1F2F)
#define ET7CTRL ECREG(EC_REG_BASE_ADDR + 0x1F30)
#define ET7PSR ECREG(EC_REG_BASE_ADDR + 0x1F31)
#define ET7CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F34)
#define ET7CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F35)
#define ET7CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F36)
#define ET8CTRL ECREG(EC_REG_BASE_ADDR + 0x1F38)
#define ET8PSR ECREG(EC_REG_BASE_ADDR + 0x1F39)
#define ET8CNTLLR ECREG(EC_REG_BASE_ADDR + 0x1F3C)
#define ET8CNTLHR ECREG(EC_REG_BASE_ADDR + 0x1F3D)
#define ET8CNTLH2R ECREG(EC_REG_BASE_ADDR + 0x1F3E)
#define ET8CNTLH3R ECREG(EC_REG_BASE_ADDR + 0x1F3F)
/* External Timer register fields */
/* External Timer 3~8 control */
#define IT8XXX2_EXT_ETXRST BIT(1)
#define IT8XXX2_EXT_ETXEN BIT(0)
/**
*