From 219a1e7f0bf27f5a346ff091e04a433771e56b8c Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Mon, 2 Jan 2017 14:06:36 +0100 Subject: [PATCH] stm32f4: Update flash to support higher sysclock frequencies stm32f411re SoC could run at system clock above 84MHz. This was not taken into account in __setup_flash function which configure flash latency depending on system clock. This is now corrected. Assert added to ease error detection. Change-Id: I49b92256d611ef464171fb1d8812a4c4d3c27ab8 Signed-off-by: Erwan Gouriou --- .../arm/soc/st_stm32/stm32f4/flash_registers.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h index 7075e4d2242..a3a464f3748 100644 --- a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h +++ b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h @@ -72,14 +72,30 @@ static inline void __setup_flash(void) if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) { regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) { + } +#ifdef CONFIG_SOC_STM32F401XE + else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) { regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) { regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; } +#elif CONFIG_SOC_STM32F411XE + else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) { + regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; + } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) { + regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; + } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) { + regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3; + } +#else + else { + __ASSERT(0, "Flash latency not set"); + } +#endif /* Make sure latency was set */ tmpreg = regs->acr.bit.latency; + } #endif /* _STM32F4X_FLASHREGISTERS_H_ */