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riscv: Rename the FE310 SoC to Sifive Freedom

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FE310 is the name of one SoC out of a range of products in the SiFive
Freedom line. The FE310 SoC port in Zephyr is compatible with all of
these products, so rename the SoC to SiFive Freedom

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit is contained in:
Nathaniel Graff 2018-08-15 15:41:21 -07:00 • committed by Anas Nashif
commit 218d7a0aa9
28 changed files with 930 additions and 930 deletions
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13
arch/riscv32/soc/riscv-privilege/fe310/Kconfig.series
View file

@ -1,13 +0,0 @@
# Kconfig - RISCV32_FE310 SOC implementation
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_RISCV32_FE310
bool "SiFive Freedom E310 SOC implementation"
depends on RISCV32
select SOC_FAMILY_RISCV_PRIVILEGE
help
Enable support for SiFive Freedom E310 SOC

16
arch/riscv32/soc/riscv-privilege/fe310/Kconfig.soc
View file

@ -1,16 +0,0 @@
# Kconfig - RISCV32_FE310 SOC configuration options
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "SiFive Freedom E310 SOC implementation"
depends on SOC_SERIES_RISCV32_FE310
config SOC_RISCV32_FE310
bool "SiFive Freedom E310 SOC implementation"
select ATOMIC_OPERATIONS_C
endchoice

0
arch/riscv32/soc/riscv-privilege/fe310/CMakeLists.txt → arch/riscv32/soc/riscv-privilege/sifive-freedom/CMakeLists.txt
View file

6
arch/riscv32/soc/riscv-privilege/fe310/Kconfig.defconfig.series → arch/riscv32/soc/riscv-privilege/sifive-freedom/Kconfig.defconfig.series
View file

@ -1,8 +1,8 @@
if SOC_SERIES_RISCV32_FE310
if SOC_SERIES_RISCV32_SIFIVE_FREEDOM
config SOC_SERIES
string
default "fe310"
default "sifive-freedom"
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
@ -44,4 +44,4 @@ config RISCV_RAM_SIZE
hex
default 0x4000
endif # SOC_SERIES_RISCV32_FE310
endif # SOC_SERIES_RISCV32_SIFIVE_FREEDOM

13
arch/riscv32/soc/riscv-privilege/sifive-freedom/Kconfig.series Normal file
View file

@ -0,0 +1,13 @@
# Kconfig - RISCV32_SIFIVE_FREEDOM SOC implementation
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_RISCV32_SIFIVE_FREEDOM
bool "SiFive Freedom SOC implementation"
depends on RISCV32
select SOC_FAMILY_RISCV_PRIVILEGE
help
Enable support for SiFive Freedom SOC

16
arch/riscv32/soc/riscv-privilege/sifive-freedom/Kconfig.soc Normal file
View file

@ -0,0 +1,16 @@
# Kconfig - RISCV32_SIFIVE_FREEDOM SOC configuration options
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "SiFive Freedom SOC implementation"
depends on SOC_SERIES_RISCV32_SIFIVE_FREEDOM
config SOC_RISCV32_SIFIVE_FREEDOM
bool "SiFive Freedom SOC implementation"
select ATOMIC_OPERATIONS_C
endchoice

2
arch/riscv32/soc/riscv-privilege/fe310/linker.ld → arch/riscv32/soc/riscv-privilege/sifive-freedom/linker.ld
View file

@ -5,7 +5,7 @@
*/
/**
* @brief Linker script for the SiFive Freedom E310 processor
* @brief Linker script for the SiFive Freedom processor
*/
#include <arch/riscv32/common/linker.ld>

28
arch/riscv32/soc/riscv-privilege/fe310/soc.h → arch/riscv32/soc/riscv-privilege/sifive-freedom/soc.h
View file

@ -5,23 +5,23 @@
*/
/**
* @file SoC configuration macros for the SiFive Freedom E310 processor
* @file SoC configuration macros for the SiFive Freedom processor
*/
#ifndef __RISCV32_FE310_SOC_H_
#define __RISCV32_FE310_SOC_H_
#ifndef __RISCV32_SIFIVE_FREEDOM_SOC_H_
#define __RISCV32_SIFIVE_FREEDOM_SOC_H_
#include <soc_common.h>
/* PINMUX Configuration */
#define FE310_PINMUX_0_BASE_ADDR (CONFIG_FE310_GPIO_0_BASE_ADDR + 0x38)
#define SIFIVE_PINMUX_0_BASE_ADDR (CONFIG_SIFIVE_GPIO_0_BASE_ADDR + 0x38)
/* PINMUX IO Hardware Functions */
#define FE310_PINMUX_IOF0 0x00
#define FE310_PINMUX_IOF1 0x01
#define SIFIVE_PINMUX_IOF0 0x00
#define SIFIVE_PINMUX_IOF1 0x01
/* PINMUX MAX PINS */
#define FE310_PINMUX_PINS 32
#define SIFIVE_PINMUX_PINS 32
/* Platform Level Interrupt Controller Configuration */
#define PLIC_PRIO_BASE_ADDR PLIC_BASE_ADDRESS
@ -38,16 +38,16 @@
#define RISCV_MTIMECMP_BASE 0x02004000
/* Always ON Domain */
#define FE310_PMUIE 0x10000140
#define FE310_PMUCAUSE 0x10000144
#define FE310_PMUSLEEP 0x10000148
#define FE310_PMUKEY 0x1000014C
#define FE310_SLEEP_KEY_VAL 0x0051F15E
#define SIFIVE_PMUIE 0x10000140
#define SIFIVE_PMUCAUSE 0x10000144
#define SIFIVE_PMUSLEEP 0x10000148
#define SIFIVE_PMUKEY 0x1000014C
#define SIFIVE_SLEEP_KEY_VAL 0x0051F15E
#define FE310_BACKUP_REG_BASE 0x10000080
#define SIFIVE_BACKUP_REG_BASE 0x10000080
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
#define RISCV_RAM_SIZE CONFIG_RISCV_RAM_SIZE
#endif /* __RISCV32_FE310_SOC_H_ */
#endif /* __RISCV32_SIFIVE_FREEDOM_SOC_H_ */

2
boards/riscv32/hifive1/Kconfig.board
View file

@ -1,4 +1,4 @@
config BOARD_HIFIVE1
bool "HiFive1 target"
depends on SOC_RISCV32_FE310
depends on SOC_RISCV32_SIFIVE_FREEDOM
select HAS_DTS

4
boards/riscv32/hifive1/board.h
View file

@ -17,8 +17,8 @@
* on other boards where the uart clock is determined dynamically
* following the PLL configuration
*/
#define uart_fe310_port_0_clk_freq 16000000
#define uart_fe310_port_1_clk_freq 16000000
#define uart_sifive_port_0_clk_freq 16000000
#define uart_sifive_port_1_clk_freq 16000000
/* LEDS configuration */
#define LED0_GPIO_PORT "gpio0"

86
boards/riscv32/hifive1/dts.fixup
View file

@ -5,51 +5,51 @@
*/
/* GPIO 0 */
#define CONFIG_FE310_GPIO_0_BASE_ADDR SIFIVE_GPIO0_10012000_BASE_ADDRESS
#define CONFIG_FE310_GPIO_0_IRQ_0 SIFIVE_GPIO0_10012000_IRQ_0
#define CONFIG_FE310_GPIO_0_IRQ_1 SIFIVE_GPIO0_10012000_IRQ_1
#define CONFIG_FE310_GPIO_0_IRQ_2 SIFIVE_GPIO0_10012000_IRQ_2
#define CONFIG_FE310_GPIO_0_IRQ_3 SIFIVE_GPIO0_10012000_IRQ_3
#define CONFIG_FE310_GPIO_0_IRQ_4 SIFIVE_GPIO0_10012000_IRQ_4
#define CONFIG_FE310_GPIO_0_IRQ_5 SIFIVE_GPIO0_10012000_IRQ_5
#define CONFIG_FE310_GPIO_0_IRQ_6 SIFIVE_GPIO0_10012000_IRQ_6
#define CONFIG_FE310_GPIO_0_IRQ_7 SIFIVE_GPIO0_10012000_IRQ_7
#define CONFIG_FE310_GPIO_0_IRQ_8 SIFIVE_GPIO0_10012000_IRQ_8
#define CONFIG_FE310_GPIO_0_IRQ_9 SIFIVE_GPIO0_10012000_IRQ_9
#define CONFIG_FE310_GPIO_0_IRQ_10 SIFIVE_GPIO0_10012000_IRQ_10
#define CONFIG_FE310_GPIO_0_IRQ_11 SIFIVE_GPIO0_10012000_IRQ_11
#define CONFIG_FE310_GPIO_0_IRQ_12 SIFIVE_GPIO0_10012000_IRQ_12
#define CONFIG_FE310_GPIO_0_IRQ_13 SIFIVE_GPIO0_10012000_IRQ_13
#define CONFIG_FE310_GPIO_0_IRQ_14 SIFIVE_GPIO0_10012000_IRQ_14
#define CONFIG_FE310_GPIO_0_IRQ_15 SIFIVE_GPIO0_10012000_IRQ_15
#define CONFIG_FE310_GPIO_0_IRQ_16 SIFIVE_GPIO0_10012000_IRQ_16
#define CONFIG_FE310_GPIO_0_IRQ_17 SIFIVE_GPIO0_10012000_IRQ_17
#define CONFIG_FE310_GPIO_0_IRQ_18 SIFIVE_GPIO0_10012000_IRQ_18
#define CONFIG_FE310_GPIO_0_IRQ_19 SIFIVE_GPIO0_10012000_IRQ_19
#define CONFIG_FE310_GPIO_0_IRQ_20 SIFIVE_GPIO0_10012000_IRQ_20
#define CONFIG_FE310_GPIO_0_IRQ_21 SIFIVE_GPIO0_10012000_IRQ_21
#define CONFIG_FE310_GPIO_0_IRQ_22 SIFIVE_GPIO0_10012000_IRQ_22
#define CONFIG_FE310_GPIO_0_IRQ_23 SIFIVE_GPIO0_10012000_IRQ_23
#define CONFIG_FE310_GPIO_0_IRQ_24 SIFIVE_GPIO0_10012000_IRQ_24
#define CONFIG_FE310_GPIO_0_IRQ_25 SIFIVE_GPIO0_10012000_IRQ_25
#define CONFIG_FE310_GPIO_0_IRQ_26 SIFIVE_GPIO0_10012000_IRQ_26
#define CONFIG_FE310_GPIO_0_IRQ_27 SIFIVE_GPIO0_10012000_IRQ_27
#define CONFIG_FE310_GPIO_0_IRQ_28 SIFIVE_GPIO0_10012000_IRQ_28
#define CONFIG_FE310_GPIO_0_IRQ_29 SIFIVE_GPIO0_10012000_IRQ_29
#define CONFIG_FE310_GPIO_0_IRQ_30 SIFIVE_GPIO0_10012000_IRQ_30
#define CONFIG_FE310_GPIO_0_IRQ_31 SIFIVE_GPIO0_10012000_IRQ_31
#define CONFIG_FE310_GPIO_0_SIZE SIFIVE_GPIO0_10012000_SIZE
#define CONFIG_SIFIVE_GPIO_0_BASE_ADDR SIFIVE_GPIO0_10012000_BASE_ADDRESS
#define CONFIG_SIFIVE_GPIO_0_IRQ_0 SIFIVE_GPIO0_10012000_IRQ_0
#define CONFIG_SIFIVE_GPIO_0_IRQ_1 SIFIVE_GPIO0_10012000_IRQ_1
#define CONFIG_SIFIVE_GPIO_0_IRQ_2 SIFIVE_GPIO0_10012000_IRQ_2
#define CONFIG_SIFIVE_GPIO_0_IRQ_3 SIFIVE_GPIO0_10012000_IRQ_3
#define CONFIG_SIFIVE_GPIO_0_IRQ_4 SIFIVE_GPIO0_10012000_IRQ_4
#define CONFIG_SIFIVE_GPIO_0_IRQ_5 SIFIVE_GPIO0_10012000_IRQ_5
#define CONFIG_SIFIVE_GPIO_0_IRQ_6 SIFIVE_GPIO0_10012000_IRQ_6
#define CONFIG_SIFIVE_GPIO_0_IRQ_7 SIFIVE_GPIO0_10012000_IRQ_7
#define CONFIG_SIFIVE_GPIO_0_IRQ_8 SIFIVE_GPIO0_10012000_IRQ_8
#define CONFIG_SIFIVE_GPIO_0_IRQ_9 SIFIVE_GPIO0_10012000_IRQ_9
#define CONFIG_SIFIVE_GPIO_0_IRQ_10 SIFIVE_GPIO0_10012000_IRQ_10
#define CONFIG_SIFIVE_GPIO_0_IRQ_11 SIFIVE_GPIO0_10012000_IRQ_11
#define CONFIG_SIFIVE_GPIO_0_IRQ_12 SIFIVE_GPIO0_10012000_IRQ_12
#define CONFIG_SIFIVE_GPIO_0_IRQ_13 SIFIVE_GPIO0_10012000_IRQ_13
#define CONFIG_SIFIVE_GPIO_0_IRQ_14 SIFIVE_GPIO0_10012000_IRQ_14
#define CONFIG_SIFIVE_GPIO_0_IRQ_15 SIFIVE_GPIO0_10012000_IRQ_15
#define CONFIG_SIFIVE_GPIO_0_IRQ_16 SIFIVE_GPIO0_10012000_IRQ_16
#define CONFIG_SIFIVE_GPIO_0_IRQ_17 SIFIVE_GPIO0_10012000_IRQ_17
#define CONFIG_SIFIVE_GPIO_0_IRQ_18 SIFIVE_GPIO0_10012000_IRQ_18
#define CONFIG_SIFIVE_GPIO_0_IRQ_19 SIFIVE_GPIO0_10012000_IRQ_19
#define CONFIG_SIFIVE_GPIO_0_IRQ_20 SIFIVE_GPIO0_10012000_IRQ_20
#define CONFIG_SIFIVE_GPIO_0_IRQ_21 SIFIVE_GPIO0_10012000_IRQ_21
#define CONFIG_SIFIVE_GPIO_0_IRQ_22 SIFIVE_GPIO0_10012000_IRQ_22
#define CONFIG_SIFIVE_GPIO_0_IRQ_23 SIFIVE_GPIO0_10012000_IRQ_23
#define CONFIG_SIFIVE_GPIO_0_IRQ_24 SIFIVE_GPIO0_10012000_IRQ_24
#define CONFIG_SIFIVE_GPIO_0_IRQ_25 SIFIVE_GPIO0_10012000_IRQ_25
#define CONFIG_SIFIVE_GPIO_0_IRQ_26 SIFIVE_GPIO0_10012000_IRQ_26
#define CONFIG_SIFIVE_GPIO_0_IRQ_27 SIFIVE_GPIO0_10012000_IRQ_27
#define CONFIG_SIFIVE_GPIO_0_IRQ_28 SIFIVE_GPIO0_10012000_IRQ_28
#define CONFIG_SIFIVE_GPIO_0_IRQ_29 SIFIVE_GPIO0_10012000_IRQ_29
#define CONFIG_SIFIVE_GPIO_0_IRQ_30 SIFIVE_GPIO0_10012000_IRQ_30
#define CONFIG_SIFIVE_GPIO_0_IRQ_31 SIFIVE_GPIO0_10012000_IRQ_31
#define CONFIG_SIFIVE_GPIO_0_SIZE SIFIVE_GPIO0_10012000_SIZE
/* UART 0 */
#define CONFIG_FE310_UART_0_BASE_ADDR SIFIVE_UART0_10013000_BASE_ADDRESS
#define CONFIG_FE310_UART_0_CURRENT_SPEED SIFIVE_UART0_10013000_CURRENT_SPEED
#define CONFIG_FE310_UART_0_IRQ_0 SIFIVE_UART0_10013000_IRQ_0
#define CONFIG_FE310_UART_0_LABEL SIFIVE_UART0_10013000_LABEL
#define CONFIG_FE310_UART_0_SIZE SIFIVE_UART0_10013000_SIZE
#define CONFIG_SIFIVE_UART_0_BASE_ADDR SIFIVE_UART0_10013000_BASE_ADDRESS
#define CONFIG_SIFIVE_UART_0_CURRENT_SPEED SIFIVE_UART0_10013000_CURRENT_SPEED
#define CONFIG_SIFIVE_UART_0_IRQ_0 SIFIVE_UART0_10013000_IRQ_0
#define CONFIG_SIFIVE_UART_0_LABEL SIFIVE_UART0_10013000_LABEL
#define CONFIG_SIFIVE_UART_0_SIZE SIFIVE_UART0_10013000_SIZE
/* UART 1 */
#define CONFIG_FE310_UART_1_BASE_ADDR SIFIVE_UART0_10023000_BASE_ADDRESS
#define CONFIG_FE310_UART_1_CURRENT_SPEED SIFIVE_UART0_10023000_CURRENT_SPEED
#define CONFIG_FE310_UART_1_IRQ_0 SIFIVE_UART0_10023000_IRQ_0
#define CONFIG_FE310_UART_1_SIZE SIFIVE_UART0_10023000_SIZE
#define CONFIG_SIFIVE_UART_1_BASE_ADDR SIFIVE_UART0_10023000_BASE_ADDRESS
#define CONFIG_SIFIVE_UART_1_CURRENT_SPEED SIFIVE_UART0_10023000_CURRENT_SPEED
#define CONFIG_SIFIVE_UART_1_IRQ_0 SIFIVE_UART0_10023000_IRQ_0
#define CONFIG_SIFIVE_UART_1_SIZE SIFIVE_UART0_10023000_SIZE

12
boards/riscv32/hifive1/hifive1_defconfig
View file

@ -1,17 +1,17 @@
CONFIG_RISCV32=y
CONFIG_SOC_SERIES_RISCV32_FE310=y
CONFIG_SOC_RISCV32_FE310=y
CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
CONFIG_BOARD_HIFIVE1=y
CONFIG_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_SERIAL=y
CONFIG_UART_FE310=y
CONFIG_UART_FE310_PORT_0=y
CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_PLIC=y
CONFIG_PINMUX=y
CONFIG_PINMUX_FE310=y
CONFIG_PINMUX_SIFIVE=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_GPIO=y
CONFIG_GPIO_FE310=y
CONFIG_GPIO_SIFIVE=y
CONFIG_BOOT_BANNER=y

18
boards/riscv32/hifive1/pinmux.c
View file

@ -12,21 +12,21 @@ static int hifive1_pinmux_init(struct device *dev)
{
ARG_UNUSED(dev);
struct device *p = device_get_binding(CONFIG_PINMUX_FE310_0_NAME);
struct device *p = device_get_binding(CONFIG_PINMUX_SIFIVE_0_NAME);
/* UART0 RX */
pinmux_pin_set(p, 16, FE310_PINMUX_IOF0);
pinmux_pin_set(p, 16, SIFIVE_PINMUX_IOF0);
/* UART0 TX */
pinmux_pin_set(p, 17, FE310_PINMUX_IOF0);
pinmux_pin_set(p, 17, SIFIVE_PINMUX_IOF0);
/* SPI1 */
pinmux_pin_set(p, 2, FE310_PINMUX_IOF0); /* SS0 */
pinmux_pin_set(p, 3, FE310_PINMUX_IOF0); /* MOSI */
pinmux_pin_set(p, 4, FE310_PINMUX_IOF0); /* MISO */
pinmux_pin_set(p, 5, FE310_PINMUX_IOF0); /* SCK */
pinmux_pin_set(p, 9, FE310_PINMUX_IOF0); /* SS2 */
pinmux_pin_set(p, 10, FE310_PINMUX_IOF0); /* SS3 */
pinmux_pin_set(p, 2, SIFIVE_PINMUX_IOF0); /* SS0 */
pinmux_pin_set(p, 3, SIFIVE_PINMUX_IOF0); /* MOSI */
pinmux_pin_set(p, 4, SIFIVE_PINMUX_IOF0); /* MISO */
pinmux_pin_set(p, 5, SIFIVE_PINMUX_IOF0); /* SCK */
pinmux_pin_set(p, 9, SIFIVE_PINMUX_IOF0); /* SS2 */
pinmux_pin_set(p, 10, SIFIVE_PINMUX_IOF0); /* SS3 */
return 0;
}

2
drivers/gpio/CMakeLists.txt
View file

@ -7,7 +7,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB gpio_cmsdk_ahb.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_DW gpio_dw.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_ESP32 gpio_esp32.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_FE310 gpio_fe310.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_SIFIVE gpio_sifive.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_GECKO gpio_gecko.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_IMX gpio_imx.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX gpio_mcux.c)

2
drivers/gpio/Kconfig
View file

@ -60,7 +60,7 @@ source "drivers/gpio/Kconfig.cc32xx"
source "drivers/gpio/Kconfig.pulpino"
source "drivers/gpio/Kconfig.fe310"
source "drivers/gpio/Kconfig.sifive"
source "drivers/gpio/Kconfig.cc2650"

80
drivers/gpio/Kconfig.fe310 → drivers/gpio/Kconfig.sifive
View file

@ -1,150 +1,150 @@
# Kconfig.fe310 - SiFive Freedom E310 GPIO configuration option
# Kconfig.fe310 - SiFive Freedom GPIO configuration option
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig GPIO_FE310
bool "SiFive Freedom E310 Processor GPIO driver"
depends on GPIO && SOC_RISCV32_FE310
menuconfig GPIO_SIFIVE
bool "SiFive Freedom Processor GPIO driver"
depends on GPIO && SOC_RISCV32_SIFIVE_FREEDOM
help
Enable driver for the SiFive Freedom E310 GPIO controller.
Enable driver for the SiFive Freedom GPIO controller.
Says n if not sure.
if GPIO_FE310
if GPIO_SIFIVE
config GPIO_FE310_GPIO_NAME
config GPIO_SIFIVE_GPIO_NAME
string "GPIO driver name"
default "gpio0"
config GPIO_FE310_0_PRIORITY
config GPIO_SIFIVE_0_PRIORITY
int "GPIO 0 interrupt priority"
default 1
config GPIO_FE310_1_PRIORITY
config GPIO_SIFIVE_1_PRIORITY
int "GPIO 1 interrupt priority"
default 1
config GPIO_FE310_2_PRIORITY
config GPIO_SIFIVE_2_PRIORITY
int "GPIO 2 interrupt priority"
default 1
config GPIO_FE310_3_PRIORITY
config GPIO_SIFIVE_3_PRIORITY
int "GPIO 3 interrupt priority"
default 1
config GPIO_FE310_4_PRIORITY
config GPIO_SIFIVE_4_PRIORITY
int "GPIO 4 interrupt priority"
default 1
config GPIO_FE310_5_PRIORITY
config GPIO_SIFIVE_5_PRIORITY
int "GPIO 5 interrupt priority"
default 1
config GPIO_FE310_6_PRIORITY
config GPIO_SIFIVE_6_PRIORITY
int "GPIO 6 interrupt priority"
default 1
config GPIO_FE310_7_PRIORITY
config GPIO_SIFIVE_7_PRIORITY
int "GPIO 7 interrupt priority"
default 1
config GPIO_FE310_8_PRIORITY
config GPIO_SIFIVE_8_PRIORITY
int "GPIO 8 interrupt priority"
default 1
config GPIO_FE310_9_PRIORITY
config GPIO_SIFIVE_9_PRIORITY
int "GPIO 9 interrupt priority"
default 1
config GPIO_FE310_10_PRIORITY
config GPIO_SIFIVE_10_PRIORITY
int "GPIO 10 interrupt priority"
default 1
config GPIO_FE310_11_PRIORITY
config GPIO_SIFIVE_11_PRIORITY
int "GPIO 11 interrupt priority"
default 1
config GPIO_FE310_12_PRIORITY
config GPIO_SIFIVE_12_PRIORITY
int "GPIO 12 interrupt priority"
default 1
config GPIO_FE310_13_PRIORITY
config GPIO_SIFIVE_13_PRIORITY
int "GPIO 13 interrupt priority"
default 1
config GPIO_FE310_14_PRIORITY
config GPIO_SIFIVE_14_PRIORITY
int "GPIO 14 interrupt priority"
default 1
config GPIO_FE310_15_PRIORITY
config GPIO_SIFIVE_15_PRIORITY
int "GPIO 15 interrupt priority"
default 1
config GPIO_FE310_16_PRIORITY
config GPIO_SIFIVE_16_PRIORITY
int "GPIO 16 interrupt priority"
default 1
config GPIO_FE310_17_PRIORITY
config GPIO_SIFIVE_17_PRIORITY
int "GPIO 17 interrupt priority"
default 1
config GPIO_FE310_18_PRIORITY
config GPIO_SIFIVE_18_PRIORITY
int "GPIO 18 interrupt priority"
default 1
config GPIO_FE310_19_PRIORITY
config GPIO_SIFIVE_19_PRIORITY
int "GPIO 19 interrupt priority"
default 1
config GPIO_FE310_20_PRIORITY
config GPIO_SIFIVE_20_PRIORITY
int "GPIO 20 interrupt priority"
default 1
config GPIO_FE310_21_PRIORITY
config GPIO_SIFIVE_21_PRIORITY
int "GPIO 21 interrupt priority"
default 1
config GPIO_FE310_22_PRIORITY
config GPIO_SIFIVE_22_PRIORITY
int "GPIO 22 interrupt priority"
default 1
config GPIO_FE310_23_PRIORITY
config GPIO_SIFIVE_23_PRIORITY
int "GPIO 23 interrupt priority"
default 1
config GPIO_FE310_24_PRIORITY
config GPIO_SIFIVE_24_PRIORITY
int "GPIO 24 interrupt priority"
default 1
config GPIO_FE310_25_PRIORITY
config GPIO_SIFIVE_25_PRIORITY
int "GPIO 25 interrupt priority"
default 1
config GPIO_FE310_26_PRIORITY
config GPIO_SIFIVE_26_PRIORITY
int "GPIO 26 interrupt priority"
default 1
config GPIO_FE310_27_PRIORITY
config GPIO_SIFIVE_27_PRIORITY
int "GPIO 27 interrupt priority"
default 1
config GPIO_FE310_28_PRIORITY
config GPIO_SIFIVE_28_PRIORITY
int "GPIO 28 interrupt priority"
default 1
config GPIO_FE310_29_PRIORITY
config GPIO_SIFIVE_29_PRIORITY
int "GPIO 29 interrupt priority"
default 1
config GPIO_FE310_30_PRIORITY
config GPIO_SIFIVE_30_PRIORITY
int "GPIO 30 interrupt priority"
default 1
config GPIO_FE310_31_PRIORITY
config GPIO_SIFIVE_31_PRIORITY
int "GPIO 31 interrupt priority"
default 1
endif # GPIO_FE310
endif # GPIO_SIFIVE

535
drivers/gpio/gpio_fe310.c
View file

@ -1,535 +0,0 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file GPIO driver for the SiFive Freedom E310 Processor
*/
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <soc.h>
#include <gpio.h>
#include <misc/util.h>
#include "gpio_utils.h"
typedef void (*fe310_cfg_func_t)(void);
/* fe310 GPIO register-set structure */
struct gpio_fe310_t {
unsigned int in_val;
unsigned int in_en;
unsigned int out_en;
unsigned int out_val;
unsigned int pue;
unsigned int ds;
unsigned int rise_ie;
unsigned int rise_ip;
unsigned int fall_ie;
unsigned int fall_ip;
unsigned int high_ie;
unsigned int high_ip;
unsigned int low_ie;
unsigned int low_ip;
unsigned int iof_en;
unsigned int iof_sel;
unsigned int invert;
};
struct gpio_fe310_config {
u32_t gpio_base_addr;
u32_t gpio_irq_base;
fe310_cfg_func_t gpio_cfg_func;
};
struct gpio_fe310_data {
/* list of callbacks */
sys_slist_t cb;
};
/* Helper Macros for GPIO */
#define DEV_GPIO_CFG(dev) \
((const struct gpio_fe310_config * const)(dev)->config->config_info)
#define DEV_GPIO(dev) \
((volatile struct gpio_fe310_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
#define DEV_GPIO_DATA(dev) \
((struct gpio_fe310_data *)(dev)->driver_data)
static void gpio_fe310_irq_handler(void *arg)
{
struct device *dev = (struct device *)arg;
struct gpio_fe310_data *data = DEV_GPIO_DATA(dev);
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
const struct gpio_fe310_config *cfg = DEV_GPIO_CFG(dev);
int pin_mask;
/* Get the pin number generating the interrupt */
pin_mask = 1 << (riscv_plic_get_irq() -
(cfg->gpio_irq_base - RISCV_MAX_GENERIC_IRQ));
/* Call the corresponding callback registered for the pin */
_gpio_fire_callbacks(&data->cb, dev, pin_mask);
/*
* Write to either the rise_ip, fall_ip, high_ip or low_ip registers
* to indicate to GPIO controller that interrupt for the corresponding
* pin has been handled.
*/
if (gpio->rise_ip & pin_mask)
gpio->rise_ip = pin_mask;
else if (gpio->fall_ip & pin_mask)
gpio->fall_ip = pin_mask;
else if (gpio->high_ip & pin_mask)
gpio->high_ip = pin_mask;
else if (gpio->low_ip & pin_mask)
gpio->low_ip = pin_mask;
}
/**
* @brief Configure pin
*
* @param dev Device structure
* @param access_op Access operation
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_fe310_config(struct device *dev,
int access_op,
u32_t pin,
int flags)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= FE310_PINMUX_PINS)
return -EINVAL;
/* Configure gpio direction */
if (flags & GPIO_DIR_OUT) {
gpio->in_en &= ~BIT(pin);
gpio->out_en |= BIT(pin);
/*
* Account for polarity only for GPIO_DIR_OUT.
* invert register handles only output gpios
*/
if (flags & GPIO_POL_INV)
gpio->invert |= BIT(pin);
else
gpio->invert &= ~BIT(pin);
} else {
gpio->out_en &= ~BIT(pin);
gpio->in_en |= BIT(pin);
/* Polarity inversion is not supported for input gpio */
if (flags & GPIO_POL_INV)
return -EINVAL;
/*
* Pull-up can be configured only for input gpios.
* Only Pull-up can be enabled or disabled.
*/
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN)
return -EINVAL;
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP)
gpio->pue |= BIT(pin);
else
gpio->pue &= ~BIT(pin);
}
/*
* Configure interrupt if GPIO_INT is set.
* Here, we just configure the gpio interrupt behavior,
* we do not enable/disable interrupt for a particular
* gpio.
* Interrupt for a gpio is:
* 1) enabled only via a call to gpio_fe310_enable_callback.
* 2) disabled only via a call to gpio_fe310_disabled_callback.
*/
if (!(flags & GPIO_INT))
return 0;
/*
* Interrupt cannot be set for GPIO_DIR_OUT
*/
if (flags & GPIO_DIR_OUT)
return -EINVAL;
/* Edge or Level triggered ? */
if (flags & GPIO_INT_EDGE) {
gpio->high_ie &= ~BIT(pin);
gpio->low_ie &= ~BIT(pin);
/* Rising Edge, Falling Edge or Double Edge ? */
if (flags & GPIO_INT_DOUBLE_EDGE) {
gpio->rise_ie |= BIT(pin);
gpio->fall_ie |= BIT(pin);
} else if (flags & GPIO_INT_ACTIVE_HIGH) {
gpio->rise_ie |= BIT(pin);
gpio->fall_ie &= ~BIT(pin);
} else {
gpio->rise_ie &= ~BIT(pin);
gpio->fall_ie |= BIT(pin);
}
} else {
gpio->rise_ie &= ~BIT(pin);
gpio->fall_ie &= ~BIT(pin);
/* Level High ? */
if (flags & GPIO_INT_ACTIVE_HIGH) {
gpio->high_ie |= BIT(pin);
gpio->low_ie &= ~BIT(pin);
} else {
gpio->high_ie &= ~BIT(pin);
gpio->low_ie |= BIT(pin);
}
}
return 0;
}
/**
* @brief Set the pin
*
* @param dev Device struct
* @param access_op Access operation
* @param pin The pin number
* @param value Value to set (0 or 1)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_fe310_write(struct device *dev,
int access_op,
u32_t pin,
u32_t value)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= FE310_PINMUX_PINS)
return -EINVAL;
/* If pin is configured as input return with error */
if (gpio->in_en & BIT(pin))
return -EINVAL;
if (value)
gpio->out_val |= BIT(pin);
else
gpio->out_val &= ~BIT(pin);
return 0;
}
/**
* @brief Read the pin
*
* @param dev Device struct
* @param access_op Access operation
* @param pin The pin number
* @param value Value of input pin(s)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_fe310_read(struct device *dev,
int access_op,
u32_t pin,
u32_t *value)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= FE310_PINMUX_PINS)
return -EINVAL;
/*
* If gpio is configured as output,
* read gpio value from out_val register,
* otherwise read gpio value from in_val register
*/
if (gpio->out_en & BIT(pin))
*value = !!(gpio->out_val & BIT(pin));
else
*value = !!(gpio->in_val & BIT(pin));
return 0;
}
static int gpio_fe310_manage_callback(struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_fe310_data *data = DEV_GPIO_DATA(dev);
_gpio_manage_callback(&data->cb, callback, set);
return 0;
}
static int gpio_fe310_enable_callback(struct device *dev,
int access_op,
u32_t pin)
{
const struct gpio_fe310_config *cfg = DEV_GPIO_CFG(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= FE310_PINMUX_PINS)
return -EINVAL;
/* Enable interrupt for the pin at PLIC level */
irq_enable(cfg->gpio_irq_base + pin);
return 0;
}
static int gpio_fe310_disable_callback(struct device *dev,
int access_op,
u32_t pin)
{
const struct gpio_fe310_config *cfg = DEV_GPIO_CFG(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= FE310_PINMUX_PINS)
return -EINVAL;
/* Disable interrupt for the pin at PLIC level */
irq_disable(cfg->gpio_irq_base + pin);
return 0;
}
static const struct gpio_driver_api gpio_fe310_driver = {
.config = gpio_fe310_config,
.write = gpio_fe310_write,
.read = gpio_fe310_read,
.manage_callback = gpio_fe310_manage_callback,
.enable_callback = gpio_fe310_enable_callback,
.disable_callback = gpio_fe310_disable_callback,
};
/**
* @brief Initialize a GPIO controller
*
* Perform basic initialization of a GPIO controller
*
* @param dev GPIO device struct
*
* @return 0
*/
static int gpio_fe310_init(struct device *dev)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
const struct gpio_fe310_config *cfg = DEV_GPIO_CFG(dev);
/* Ensure that all gpio registers are reset to 0 initially */
gpio->in_en = 0;
gpio->out_en = 0;
gpio->pue = 0;
gpio->rise_ie = 0;
gpio->fall_ie = 0;
gpio->high_ie = 0;
gpio->low_ie = 0;
gpio->invert = 0;
/* Setup IRQ handler for each gpio pin */
cfg->gpio_cfg_func();
return 0;
}
static void gpio_fe310_cfg_0(void);
static const struct gpio_fe310_config gpio_fe310_config0 = {
.gpio_base_addr = CONFIG_FE310_GPIO_0_BASE_ADDR,
.gpio_irq_base = CONFIG_FE310_GPIO_0_IRQ_0,
.gpio_cfg_func = gpio_fe310_cfg_0,
};
static struct gpio_fe310_data gpio_fe310_data0;
DEVICE_AND_API_INIT(gpio_fe310_0, CONFIG_GPIO_FE310_GPIO_NAME,
gpio_fe310_init,
&gpio_fe310_data0, &gpio_fe310_config0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_fe310_driver);
static void gpio_fe310_cfg_0(void)
{
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_0,
CONFIG_GPIO_FE310_0_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_1,
CONFIG_GPIO_FE310_1_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_2,
CONFIG_GPIO_FE310_2_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_3,
CONFIG_GPIO_FE310_3_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_4,
CONFIG_GPIO_FE310_4_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_5,
CONFIG_GPIO_FE310_5_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_6,
CONFIG_GPIO_FE310_6_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_7,
CONFIG_GPIO_FE310_7_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_8,
CONFIG_GPIO_FE310_8_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_9,
CONFIG_GPIO_FE310_9_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_10,
CONFIG_GPIO_FE310_10_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_11,
CONFIG_GPIO_FE310_11_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_12,
CONFIG_GPIO_FE310_12_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_13,
CONFIG_GPIO_FE310_13_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_14,
CONFIG_GPIO_FE310_14_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_15,
CONFIG_GPIO_FE310_15_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_16,
CONFIG_GPIO_FE310_16_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_17,
CONFIG_GPIO_FE310_17_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_18,
CONFIG_GPIO_FE310_18_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_19,
CONFIG_GPIO_FE310_19_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_20,
CONFIG_GPIO_FE310_20_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_21,
CONFIG_GPIO_FE310_21_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_22,
CONFIG_GPIO_FE310_22_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_23,
CONFIG_GPIO_FE310_23_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_24,
CONFIG_GPIO_FE310_24_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_25,
CONFIG_GPIO_FE310_25_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_26,
CONFIG_GPIO_FE310_26_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_27,
CONFIG_GPIO_FE310_27_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_28,
CONFIG_GPIO_FE310_28_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_29,
CONFIG_GPIO_FE310_29_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_30,
CONFIG_GPIO_FE310_30_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
IRQ_CONNECT(CONFIG_FE310_GPIO_0_IRQ_31,
CONFIG_GPIO_FE310_31_PRIORITY,
gpio_fe310_irq_handler,
DEVICE_GET(gpio_fe310_0),
0);
}

535
drivers/gpio/gpio_sifive.c Normal file
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@ -0,0 +1,535 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file GPIO driver for the SiFive Freedom Processor
*/
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <soc.h>
#include <gpio.h>
#include <misc/util.h>
#include "gpio_utils.h"
typedef void (*sifive_cfg_func_t)(void);
/* sifive GPIO register-set structure */
struct gpio_sifive_t {
unsigned int in_val;
unsigned int in_en;
unsigned int out_en;
unsigned int out_val;
unsigned int pue;
unsigned int ds;
unsigned int rise_ie;
unsigned int rise_ip;
unsigned int fall_ie;
unsigned int fall_ip;
unsigned int high_ie;
unsigned int high_ip;
unsigned int low_ie;
unsigned int low_ip;
unsigned int iof_en;
unsigned int iof_sel;
unsigned int invert;
};
struct gpio_sifive_config {
u32_t gpio_base_addr;
u32_t gpio_irq_base;
sifive_cfg_func_t gpio_cfg_func;
};
struct gpio_sifive_data {
/* list of callbacks */
sys_slist_t cb;
};
/* Helper Macros for GPIO */
#define DEV_GPIO_CFG(dev) \
((const struct gpio_sifive_config * const)(dev)->config->config_info)
#define DEV_GPIO(dev) \
((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
#define DEV_GPIO_DATA(dev) \
((struct gpio_sifive_data *)(dev)->driver_data)
static void gpio_sifive_irq_handler(void *arg)
{
struct device *dev = (struct device *)arg;
struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
int pin_mask;
/* Get the pin number generating the interrupt */
pin_mask = 1 << (riscv_plic_get_irq() -
(cfg->gpio_irq_base - RISCV_MAX_GENERIC_IRQ));
/* Call the corresponding callback registered for the pin */
_gpio_fire_callbacks(&data->cb, dev, pin_mask);
/*
* Write to either the rise_ip, fall_ip, high_ip or low_ip registers
* to indicate to GPIO controller that interrupt for the corresponding
* pin has been handled.
*/
if (gpio->rise_ip & pin_mask)
gpio->rise_ip = pin_mask;
else if (gpio->fall_ip & pin_mask)
gpio->fall_ip = pin_mask;
else if (gpio->high_ip & pin_mask)
gpio->high_ip = pin_mask;
else if (gpio->low_ip & pin_mask)
gpio->low_ip = pin_mask;
}
/**
* @brief Configure pin
*
* @param dev Device structure
* @param access_op Access operation
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_sifive_config(struct device *dev,
int access_op,
u32_t pin,
int flags)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= SIFIVE_PINMUX_PINS)
return -EINVAL;
/* Configure gpio direction */
if (flags & GPIO_DIR_OUT) {
gpio->in_en &= ~BIT(pin);
gpio->out_en |= BIT(pin);
/*
* Account for polarity only for GPIO_DIR_OUT.
* invert register handles only output gpios
*/
if (flags & GPIO_POL_INV)
gpio->invert |= BIT(pin);
else
gpio->invert &= ~BIT(pin);
} else {
gpio->out_en &= ~BIT(pin);
gpio->in_en |= BIT(pin);
/* Polarity inversion is not supported for input gpio */
if (flags & GPIO_POL_INV)
return -EINVAL;
/*
* Pull-up can be configured only for input gpios.
* Only Pull-up can be enabled or disabled.
*/
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN)
return -EINVAL;
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP)
gpio->pue |= BIT(pin);
else
gpio->pue &= ~BIT(pin);
}
/*
* Configure interrupt if GPIO_INT is set.
* Here, we just configure the gpio interrupt behavior,
* we do not enable/disable interrupt for a particular
* gpio.
* Interrupt for a gpio is:
* 1) enabled only via a call to gpio_sifive_enable_callback.
* 2) disabled only via a call to gpio_sifive_disabled_callback.
*/
if (!(flags & GPIO_INT))
return 0;
/*
* Interrupt cannot be set for GPIO_DIR_OUT
*/
if (flags & GPIO_DIR_OUT)
return -EINVAL;
/* Edge or Level triggered ? */
if (flags & GPIO_INT_EDGE) {
gpio->high_ie &= ~BIT(pin);
gpio->low_ie &= ~BIT(pin);
/* Rising Edge, Falling Edge or Double Edge ? */
if (flags & GPIO_INT_DOUBLE_EDGE) {
gpio->rise_ie |= BIT(pin);
gpio->fall_ie |= BIT(pin);
} else if (flags & GPIO_INT_ACTIVE_HIGH) {
gpio->rise_ie |= BIT(pin);
gpio->fall_ie &= ~BIT(pin);
} else {
gpio->rise_ie &= ~BIT(pin);
gpio->fall_ie |= BIT(pin);
}
} else {
gpio->rise_ie &= ~BIT(pin);
gpio->fall_ie &= ~BIT(pin);
/* Level High ? */
if (flags & GPIO_INT_ACTIVE_HIGH) {
gpio->high_ie |= BIT(pin);
gpio->low_ie &= ~BIT(pin);
} else {
gpio->high_ie &= ~BIT(pin);
gpio->low_ie |= BIT(pin);
}
}
return 0;
}
/**
* @brief Set the pin
*
* @param dev Device struct
* @param access_op Access operation
* @param pin The pin number
* @param value Value to set (0 or 1)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_sifive_write(struct device *dev,
int access_op,
u32_t pin,
u32_t value)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= SIFIVE_PINMUX_PINS)
return -EINVAL;
/* If pin is configured as input return with error */
if (gpio->in_en & BIT(pin))
return -EINVAL;
if (value)
gpio->out_val |= BIT(pin);
else
gpio->out_val &= ~BIT(pin);
return 0;
}
/**
* @brief Read the pin
*
* @param dev Device struct
* @param access_op Access operation
* @param pin The pin number
* @param value Value of input pin(s)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_sifive_read(struct device *dev,
int access_op,
u32_t pin,
u32_t *value)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= SIFIVE_PINMUX_PINS)
return -EINVAL;
/*
* If gpio is configured as output,
* read gpio value from out_val register,
* otherwise read gpio value from in_val register
*/
if (gpio->out_en & BIT(pin))
*value = !!(gpio->out_val & BIT(pin));
else
*value = !!(gpio->in_val & BIT(pin));
return 0;
}
static int gpio_sifive_manage_callback(struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
_gpio_manage_callback(&data->cb, callback, set);
return 0;
}
static int gpio_sifive_enable_callback(struct device *dev,
int access_op,
u32_t pin)
{
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= SIFIVE_PINMUX_PINS)
return -EINVAL;
/* Enable interrupt for the pin at PLIC level */
irq_enable(cfg->gpio_irq_base + pin);
return 0;
}
static int gpio_sifive_disable_callback(struct device *dev,
int access_op,
u32_t pin)
{
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
if (access_op != GPIO_ACCESS_BY_PIN)
return -ENOTSUP;
if (pin >= SIFIVE_PINMUX_PINS)
return -EINVAL;
/* Disable interrupt for the pin at PLIC level */
irq_disable(cfg->gpio_irq_base + pin);
return 0;
}
static const struct gpio_driver_api gpio_sifive_driver = {
.config = gpio_sifive_config,
.write = gpio_sifive_write,
.read = gpio_sifive_read,
.manage_callback = gpio_sifive_manage_callback,
.enable_callback = gpio_sifive_enable_callback,
.disable_callback = gpio_sifive_disable_callback,
};
/**
* @brief Initialize a GPIO controller
*
* Perform basic initialization of a GPIO controller
*
* @param dev GPIO device struct
*
* @return 0
*/
static int gpio_sifive_init(struct device *dev)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
/* Ensure that all gpio registers are reset to 0 initially */
gpio->in_en = 0;
gpio->out_en = 0;
gpio->pue = 0;
gpio->rise_ie = 0;
gpio->fall_ie = 0;
gpio->high_ie = 0;
gpio->low_ie = 0;
gpio->invert = 0;
/* Setup IRQ handler for each gpio pin */
cfg->gpio_cfg_func();
return 0;
}
static void gpio_sifive_cfg_0(void);
static const struct gpio_sifive_config gpio_sifive_config0 = {
.gpio_base_addr = CONFIG_SIFIVE_GPIO_0_BASE_ADDR,
.gpio_irq_base = CONFIG_SIFIVE_GPIO_0_IRQ_0,
.gpio_cfg_func = gpio_sifive_cfg_0,
};
static struct gpio_sifive_data gpio_sifive_data0;
DEVICE_AND_API_INIT(gpio_sifive_0, CONFIG_GPIO_SIFIVE_GPIO_NAME,
gpio_sifive_init,
&gpio_sifive_data0, &gpio_sifive_config0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_sifive_driver);
static void gpio_sifive_cfg_0(void)
{
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_0,
CONFIG_GPIO_SIFIVE_0_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_1,
CONFIG_GPIO_SIFIVE_1_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_2,
CONFIG_GPIO_SIFIVE_2_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_3,
CONFIG_GPIO_SIFIVE_3_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_4,
CONFIG_GPIO_SIFIVE_4_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_5,
CONFIG_GPIO_SIFIVE_5_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_6,
CONFIG_GPIO_SIFIVE_6_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_7,
CONFIG_GPIO_SIFIVE_7_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_8,
CONFIG_GPIO_SIFIVE_8_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_9,
CONFIG_GPIO_SIFIVE_9_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_10,
CONFIG_GPIO_SIFIVE_10_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_11,
CONFIG_GPIO_SIFIVE_11_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_12,
CONFIG_GPIO_SIFIVE_12_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_13,
CONFIG_GPIO_SIFIVE_13_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_14,
CONFIG_GPIO_SIFIVE_14_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_15,
CONFIG_GPIO_SIFIVE_15_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_16,
CONFIG_GPIO_SIFIVE_16_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_17,
CONFIG_GPIO_SIFIVE_17_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_18,
CONFIG_GPIO_SIFIVE_18_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_19,
CONFIG_GPIO_SIFIVE_19_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_20,
CONFIG_GPIO_SIFIVE_20_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_21,
CONFIG_GPIO_SIFIVE_21_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_22,
CONFIG_GPIO_SIFIVE_22_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_23,
CONFIG_GPIO_SIFIVE_23_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_24,
CONFIG_GPIO_SIFIVE_24_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_25,
CONFIG_GPIO_SIFIVE_25_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_26,
CONFIG_GPIO_SIFIVE_26_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_27,
CONFIG_GPIO_SIFIVE_27_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_28,
CONFIG_GPIO_SIFIVE_28_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_29,
CONFIG_GPIO_SIFIVE_29_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_30,
CONFIG_GPIO_SIFIVE_30_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
IRQ_CONNECT(CONFIG_SIFIVE_GPIO_0_IRQ_31,
CONFIG_GPIO_SIFIVE_31_PRIORITY,
gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0),
0);
}

2
drivers/pinmux/CMakeLists.txt
View file

@ -1,7 +1,7 @@
# Board initialization
zephyr_sources_ifdef(CONFIG_PINMUX_CC2650 pinmux_cc2650.c)
zephyr_sources_ifdef(CONFIG_PINMUX_ESP32 pinmux_esp32.c)
zephyr_sources_ifdef(CONFIG_PINMUX_FE310 pinmux_fe310.c)
zephyr_sources_ifdef(CONFIG_PINMUX_SIFIVE pinmux_sifive.c)
zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c)
zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC pinmux_mcux_lpc.c)
zephyr_sources_ifdef(CONFIG_PINMUX_QMSI pinmux_qmsi.c)

2
drivers/pinmux/Kconfig
View file

@ -51,7 +51,7 @@ source "drivers/pinmux/Kconfig.stm32"
source "drivers/pinmux/Kconfig.beetle"
source "drivers/pinmux/Kconfig.fe310"
source "drivers/pinmux/Kconfig.sifive"
source "drivers/pinmux/Kconfig.cc2650"

20
drivers/pinmux/Kconfig.fe310
View file

@ -1,20 +0,0 @@
# Kconfig.fe310 - PINMUX configuration options for SiFive Freedom E310 SOC
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig PINMUX_FE310
bool "SiFive Freedom E310 SOC pinmux driver"
depends on PINMUX && SOC_SERIES_RISCV32_FE310
help
Enable driver for the SiFive Freedom E310 SOC pinmux driver
if PINMUX_FE310
config PINMUX_FE310_0_NAME
string "FE310 pinmux 0 driver name"
default "pinmux0"
endif # PINMUX_FE310

20
drivers/pinmux/Kconfig.sifive Normal file
View file

@ -0,0 +1,20 @@
# Kconfig.fe310 - PINMUX configuration options for SiFive Freedom SOC
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig PINMUX_SIFIVE
bool "SiFive Freedom SOC pinmux driver"
depends on PINMUX && SOC_SERIES_RISCV32_SIFIVE_FREEDOM
help
Enable driver for the SiFive Freedom SOC pinmux driver
if PINMUX_SIFIVE
config PINMUX_SIFIVE_0_NAME
string "SIFIVE pinmux 0 driver name"
default "pinmux0"
endif # PINMUX_SIFIVE

100
drivers/pinmux/pinmux_fe310.c
View file

@ -1,100 +0,0 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief PINMUX driver for the SiFive Freedom E310 Processor
*/
#include <errno.h>
#include <device.h>
#include <pinmux.h>
#include <soc.h>
struct pinmux_fe310_config {
u32_t base;
};
struct pinmux_fe310_regs_t {
u32_t iof_en;
u32_t iof_sel;
};
#define DEV_CFG(dev) \
((const struct pinmux_fe310_config * const) \
(dev)->config->config_info)
#define DEV_PINMUX(dev) \
((struct pinmux_fe310_regs_t *)(DEV_CFG(dev))->base)
static int pinmux_fe310_set(struct device *dev, u32_t pin, u32_t func)
{
volatile struct pinmux_fe310_regs_t *pinmux = DEV_PINMUX(dev);
if (func > FE310_PINMUX_IOF1 ||
pin >= FE310_PINMUX_PINS)
return -EINVAL;
if (func == FE310_PINMUX_IOF1)
pinmux->iof_sel |= (FE310_PINMUX_IOF1 << pin);
else
pinmux->iof_sel &= ~(FE310_PINMUX_IOF1 << pin);
/* Enable IO function for this pin */
pinmux->iof_en |= (1 << pin);
return 0;
}
static int pinmux_fe310_get(struct device *dev, u32_t pin, u32_t *func)
{
volatile struct pinmux_fe310_regs_t *pinmux = DEV_PINMUX(dev);
if (pin >= FE310_PINMUX_PINS ||
func == NULL)
return -EINVAL;
*func = (pinmux->iof_sel & (FE310_PINMUX_IOF1 << pin)) ?
FE310_PINMUX_IOF1 : FE310_PINMUX_IOF0;
return 0;
}
static int pinmux_fe310_pullup(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}
static int pinmux_fe310_input(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}
static int pinmux_fe310_init(struct device *dev)
{
volatile struct pinmux_fe310_regs_t *pinmux = DEV_PINMUX(dev);
/* Ensure that all pins are disabled initially */
pinmux->iof_en = 0x0;
return 0;
}
static const struct pinmux_driver_api pinmux_fe310_driver_api = {
.set = pinmux_fe310_set,
.get = pinmux_fe310_get,
.pullup = pinmux_fe310_pullup,
.input = pinmux_fe310_input,
};
static const struct pinmux_fe310_config pinmux_fe310_0_config = {
.base = FE310_PINMUX_0_BASE_ADDR,
};
DEVICE_AND_API_INIT(pinmux_fe310_0, CONFIG_PINMUX_FE310_0_NAME,
&pinmux_fe310_init, NULL,
&pinmux_fe310_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_fe310_driver_api);

100
drivers/pinmux/pinmux_sifive.c Normal file
View file

@ -0,0 +1,100 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief PINMUX driver for the SiFive Freedom Processor
*/
#include <errno.h>
#include <device.h>
#include <pinmux.h>
#include <soc.h>
struct pinmux_sifive_config {
u32_t base;
};
struct pinmux_sifive_regs_t {
u32_t iof_en;
u32_t iof_sel;
};
#define DEV_CFG(dev) \
((const struct pinmux_sifive_config * const) \
(dev)->config->config_info)
#define DEV_PINMUX(dev) \
((struct pinmux_sifive_regs_t *)(DEV_CFG(dev))->base)
static int pinmux_sifive_set(struct device *dev, u32_t pin, u32_t func)
{
volatile struct pinmux_sifive_regs_t *pinmux = DEV_PINMUX(dev);
if (func > SIFIVE_PINMUX_IOF1 ||
pin >= SIFIVE_PINMUX_PINS)
return -EINVAL;
if (func == SIFIVE_PINMUX_IOF1)
pinmux->iof_sel |= (SIFIVE_PINMUX_IOF1 << pin);
else
pinmux->iof_sel &= ~(SIFIVE_PINMUX_IOF1 << pin);
/* Enable IO function for this pin */
pinmux->iof_en |= (1 << pin);
return 0;
}
static int pinmux_sifive_get(struct device *dev, u32_t pin, u32_t *func)
{
volatile struct pinmux_sifive_regs_t *pinmux = DEV_PINMUX(dev);
if (pin >= SIFIVE_PINMUX_PINS ||
func == NULL)
return -EINVAL;
*func = (pinmux->iof_sel & (SIFIVE_PINMUX_IOF1 << pin)) ?
SIFIVE_PINMUX_IOF1 : SIFIVE_PINMUX_IOF0;
return 0;
}
static int pinmux_sifive_pullup(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}
static int pinmux_sifive_input(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}
static int pinmux_sifive_init(struct device *dev)
{
volatile struct pinmux_sifive_regs_t *pinmux = DEV_PINMUX(dev);
/* Ensure that all pins are disabled initially */
pinmux->iof_en = 0x0;
return 0;
}
static const struct pinmux_driver_api pinmux_sifive_driver_api = {
.set = pinmux_sifive_set,
.get = pinmux_sifive_get,
.pullup = pinmux_sifive_pullup,
.input = pinmux_sifive_input,
};
static const struct pinmux_sifive_config pinmux_sifive_0_config = {
.base = SIFIVE_PINMUX_0_BASE_ADDR,
};
DEVICE_AND_API_INIT(pinmux_sifive_0, CONFIG_PINMUX_SIFIVE_0_NAME,
&pinmux_sifive_init, NULL,
&pinmux_sifive_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_sifive_driver_api);

2
drivers/serial/CMakeLists.txt
View file

@ -4,7 +4,7 @@ zephyr_library_sources_if_kconfig(uart_imx.c)
zephyr_library_sources_if_kconfig(uart_cc32xx.c)
zephyr_library_sources_if_kconfig(uart_cmsdk_apb.c)
zephyr_library_sources_if_kconfig(uart_esp32.c)
zephyr_library_sources_if_kconfig(uart_fe310.c)
zephyr_library_sources_if_kconfig(uart_sifive.c)
zephyr_library_sources_if_kconfig(uart_gecko.c)
zephyr_library_sources_if_kconfig(uart_mcux.c)
zephyr_library_sources_if_kconfig(uart_mcux_lpuart.c)

2
drivers/serial/Kconfig
View file

@ -91,7 +91,7 @@ source "drivers/serial/Kconfig.cmsdk_apb"
source "drivers/serial/Kconfig.riscv_qemu"
source "drivers/serial/Kconfig.fe310"
source "drivers/serial/Kconfig.sifive"
source "drivers/serial/Kconfig.esp32"

46
drivers/serial/Kconfig.fe310 → drivers/serial/Kconfig.sifive
View file

@ -1,74 +1,74 @@
# Kconfig.fe310 - SiFive Freedom E310 UART configuration option
# Kconfig.fe310 - SiFive Freedom UART configuration option
#
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig UART_FE310
bool "SiFive Freedom E310 serial driver"
depends on SOC_RISCV32_FE310
menuconfig UART_SIFIVE
bool "SiFive Freedom serial driver"
depends on SOC_RISCV32_SIFIVE_FREEDOM
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the SiFive Freedom E310 serial driver.
This option enables the SiFive Freedom serial driver.
# ---------- Port 0 ----------
menuconfig UART_FE310_PORT_0
bool "Enable FE310 Port 0"
depends on UART_FE310
menuconfig UART_SIFIVE_PORT_0
bool "Enable SIFIVE Port 0"
depends on UART_SIFIVE
help
This tells the driver to configure the UART port at boot, depending on
the additional configure options below.
config UART_FE310_PORT_0_IRQ_PRIORITY
config UART_SIFIVE_PORT_0_IRQ_PRIORITY
int "Port 0 Interrupt Priority"
default 1
depends on UART_FE310_PORT_0
depends on UART_SIFIVE_PORT_0
help
Port 0 Interrupt Priority
config UART_FE310_PORT_0_RXCNT_IRQ
config UART_SIFIVE_PORT_0_RXCNT_IRQ
int "Port 0 RX Interrupt Threshold Count"
default 0
depends on UART_FE310_PORT_0
depends on UART_SIFIVE_PORT_0
help
Port 0 RX Threshold at which the RX FIFO interrupt triggers.
config UART_FE310_PORT_0_TXCNT_IRQ
config UART_SIFIVE_PORT_0_TXCNT_IRQ
int "Port 0 TX Interrupt Threshold Count"
default 0
depends on UART_FE310_PORT_0
depends on UART_SIFIVE_PORT_0
help
Port 0 TX Threshold at which the TX FIFO interrupt triggers.
# ---------- Port 1 ----------
menuconfig UART_FE310_PORT_1
bool "Enable FE310 Port 1"
depends on UART_FE310
menuconfig UART_SIFIVE_PORT_1
bool "Enable SIFIVE Port 1"
depends on UART_SIFIVE
help
This tells the driver to configure the UART port at boot, depending on
the additional configure options below.
config UART_FE310_PORT_1_IRQ_PRIORITY
config UART_SIFIVE_PORT_1_IRQ_PRIORITY
int "Port 1 Interrupt Priority"
default 1
depends on UART_FE310_PORT_1
depends on UART_SIFIVE_PORT_1
help
Port 1 Interrupt Priority
config UART_FE310_PORT_1_RXCNT_IRQ
config UART_SIFIVE_PORT_1_RXCNT_IRQ
int "Port 0 RX Interrupt Threshold Count"
default 0
depends on UART_FE310_PORT_1
depends on UART_SIFIVE_PORT_1
help
Port 1 RX Threshold at which the RX FIFO interrupt triggers.
config UART_FE310_PORT_1_TXCNT_IRQ
config UART_SIFIVE_PORT_1_TXCNT_IRQ
int "Port 1 TX Interrupt Threshold Count"
default 0
depends on UART_FE310_PORT_1
depends on UART_SIFIVE_PORT_1
help
Port 1 TX Threshold at which the TX FIFO interrupt triggers.

196
drivers/serial/uart_fe310.c → drivers/serial/uart_sifive.c
View file

@ -5,7 +5,7 @@
*/
/**
* @brief UART driver for the SiFive Freedom E310 Processor
* @brief UART driver for the SiFive Freedom Processor
*/
#include <kernel.h>
@ -31,7 +31,7 @@
*/
#define CTRL_CNT(x) (((x) & 0x07) << 16)
struct uart_fe310_regs_t {
struct uart_sifive_regs_t {
u32_t tx;
u32_t rx;
u32_t txctrl;
@ -45,7 +45,7 @@ struct uart_fe310_regs_t {
typedef void (*irq_cfg_func_t)(void);
#endif
struct uart_fe310_device_config {
struct uart_sifive_device_config {
u32_t port;
u32_t sys_clk_freq;
u32_t baud_rate;
@ -56,7 +56,7 @@ struct uart_fe310_device_config {
#endif
};
struct uart_fe310_data {
struct uart_sifive_data {
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t callback;
void *cb_data;
@ -64,12 +64,12 @@ struct uart_fe310_data {
};
#define DEV_CFG(dev) \
((const struct uart_fe310_device_config * const) \
((const struct uart_sifive_device_config * const) \
(dev)->config->config_info)
#define DEV_UART(dev) \
((struct uart_fe310_regs_t *)(DEV_CFG(dev))->port)
((struct uart_sifive_regs_t *)(DEV_CFG(dev))->port)
#define DEV_DATA(dev) \
((struct uart_fe310_data * const)(dev)->driver_data)
((struct uart_sifive_data * const)(dev)->driver_data)
/**
* @brief Output a character in polled mode.
@ -81,10 +81,10 @@ struct uart_fe310_data {
*
* @return Sent character
*/
static unsigned char uart_fe310_poll_out(struct device *dev,
static unsigned char uart_sifive_poll_out(struct device *dev,
unsigned char c)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
/* Wait while TX FIFO is full */
while (uart->tx & TXDATA_FULL)
@ -103,9 +103,9 @@ static unsigned char uart_fe310_poll_out(struct device *dev,
*
* @return 0 if a character arrived, -1 if the input buffer if empty.
*/
static int uart_fe310_poll_in(struct device *dev, unsigned char *c)
static int uart_sifive_poll_in(struct device *dev, unsigned char *c)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
u32_t val = uart->rx;
if (val & RXDATA_EMPTY)
@ -127,11 +127,11 @@ static int uart_fe310_poll_in(struct device *dev, unsigned char *c)
*
* @return Number of bytes sent
*/
static int uart_fe310_fifo_fill(struct device *dev,
static int uart_sifive_fifo_fill(struct device *dev,
const u8_t *tx_data,
int size)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
int i;
for (i = 0; i < size && !(uart->tx & TXDATA_FULL); i++)
@ -149,11 +149,11 @@ static int uart_fe310_fifo_fill(struct device *dev,
*
* @return Number of bytes read
*/
static int uart_fe310_fifo_read(struct device *dev,
static int uart_sifive_fifo_read(struct device *dev,
u8_t *rx_data,
const int size)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
int i;
u32_t val;
@ -176,9 +176,9 @@ static int uart_fe310_fifo_read(struct device *dev,
*
* @return N/A
*/
static void uart_fe310_irq_tx_enable(struct device *dev)
static void uart_sifive_irq_tx_enable(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie |= IE_TXWM;
}
@ -190,9 +190,9 @@ static void uart_fe310_irq_tx_enable(struct device *dev)
*
* @return N/A
*/
static void uart_fe310_irq_tx_disable(struct device *dev)
static void uart_sifive_irq_tx_disable(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie &= ~IE_TXWM;
}
@ -204,9 +204,9 @@ static void uart_fe310_irq_tx_disable(struct device *dev)
*
* @return 1 if an IRQ is ready, 0 otherwise
*/
static int uart_fe310_irq_tx_ready(struct device *dev)
static int uart_sifive_irq_tx_ready(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
return !!(uart->ip & IE_TXWM);
}
@ -218,9 +218,9 @@ static int uart_fe310_irq_tx_ready(struct device *dev)
*
* @return 1 if nothing remains to be transmitted, 0 otherwise
*/
static int uart_fe310_irq_tx_complete(struct device *dev)
static int uart_sifive_irq_tx_complete(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
/*
* No TX EMTPY flag for this controller,
@ -236,9 +236,9 @@ static int uart_fe310_irq_tx_complete(struct device *dev)
*
* @return N/A
*/
static void uart_fe310_irq_rx_enable(struct device *dev)
static void uart_sifive_irq_rx_enable(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie |= IE_RXWM;
}
@ -250,9 +250,9 @@ static void uart_fe310_irq_rx_enable(struct device *dev)
*
* @return N/A
*/
static void uart_fe310_irq_rx_disable(struct device *dev)
static void uart_sifive_irq_rx_disable(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie &= ~IE_RXWM;
}
@ -264,20 +264,20 @@ static void uart_fe310_irq_rx_disable(struct device *dev)
*
* @return 1 if an IRQ is ready, 0 otherwise
*/
static int uart_fe310_irq_rx_ready(struct device *dev)
static int uart_sifive_irq_rx_ready(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
return !!(uart->ip & IE_RXWM);
}
/* No error interrupt for this controller */
static void uart_fe310_irq_err_enable(struct device *dev)
static void uart_sifive_irq_err_enable(struct device *dev)
{
ARG_UNUSED(dev);
}
static void uart_fe310_irq_err_disable(struct device *dev)
static void uart_sifive_irq_err_disable(struct device *dev)
{
ARG_UNUSED(dev);
}
@ -289,14 +289,14 @@ static void uart_fe310_irq_err_disable(struct device *dev)
*
* @return 1 if an IRQ is pending, 0 otherwise
*/
static int uart_fe310_irq_is_pending(struct device *dev)
static int uart_sifive_irq_is_pending(struct device *dev)
{
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
return !!(uart->ip & (IE_RXWM | IE_TXWM));
}
static int uart_fe310_irq_update(struct device *dev)
static int uart_sifive_irq_update(struct device *dev)
{
return 1;
}
@ -309,20 +309,20 @@ static int uart_fe310_irq_update(struct device *dev)
*
* @return N/A
*/
static void uart_fe310_irq_callback_set(struct device *dev,
static void uart_sifive_irq_callback_set(struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct uart_fe310_data *data = DEV_DATA(dev);
struct uart_sifive_data *data = DEV_DATA(dev);
data->callback = cb;
data->cb_data = cb_data;
}
static void uart_fe310_irq_handler(void *arg)
static void uart_sifive_irq_handler(void *arg)
{
struct device *dev = (struct device *)arg;
struct uart_fe310_data *data = DEV_DATA(dev);
struct uart_sifive_data *data = DEV_DATA(dev);
if (data->callback)
data->callback(data->cb_data);
@ -331,10 +331,10 @@ static void uart_fe310_irq_handler(void *arg)
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static int uart_fe310_init(struct device *dev)
static int uart_sifive_init(struct device *dev)
{
const struct uart_fe310_device_config * const cfg = DEV_CFG(dev);
volatile struct uart_fe310_regs_t *uart = DEV_UART(dev);
const struct uart_sifive_device_config * const cfg = DEV_CFG(dev);
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
/* Enable TX and RX channels */
uart->txctrl = TXCTRL_TXEN | CTRL_CNT(cfg->rxcnt_irq);
@ -354,102 +354,102 @@ static int uart_fe310_init(struct device *dev)
return 0;
}
static const struct uart_driver_api uart_fe310_driver_api = {
.poll_in = uart_fe310_poll_in,
.poll_out = uart_fe310_poll_out,
static const struct uart_driver_api uart_sifive_driver_api = {
.poll_in = uart_sifive_poll_in,
.poll_out = uart_sifive_poll_out,
.err_check = NULL,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = uart_fe310_fifo_fill,
.fifo_read = uart_fe310_fifo_read,
.irq_tx_enable = uart_fe310_irq_tx_enable,
.irq_tx_disable = uart_fe310_irq_tx_disable,
.irq_tx_ready = uart_fe310_irq_tx_ready,
.irq_tx_complete = uart_fe310_irq_tx_complete,
.irq_rx_enable = uart_fe310_irq_rx_enable,
.irq_rx_disable = uart_fe310_irq_rx_disable,
.irq_rx_ready = uart_fe310_irq_rx_ready,
.irq_err_enable = uart_fe310_irq_err_enable,
.irq_err_disable = uart_fe310_irq_err_disable,
.irq_is_pending = uart_fe310_irq_is_pending,
.irq_update = uart_fe310_irq_update,
.irq_callback_set = uart_fe310_irq_callback_set,
.fifo_fill = uart_sifive_fifo_fill,
.fifo_read = uart_sifive_fifo_read,
.irq_tx_enable = uart_sifive_irq_tx_enable,
.irq_tx_disable = uart_sifive_irq_tx_disable,
.irq_tx_ready = uart_sifive_irq_tx_ready,
.irq_tx_complete = uart_sifive_irq_tx_complete,
.irq_rx_enable = uart_sifive_irq_rx_enable,
.irq_rx_disable = uart_sifive_irq_rx_disable,
.irq_rx_ready = uart_sifive_irq_rx_ready,
.irq_err_enable = uart_sifive_irq_err_enable,
.irq_err_disable = uart_sifive_irq_err_disable,
.irq_is_pending = uart_sifive_irq_is_pending,
.irq_update = uart_sifive_irq_update,
.irq_callback_set = uart_sifive_irq_callback_set,
#endif
};
#ifdef CONFIG_UART_FE310_PORT_0
#ifdef CONFIG_UART_SIFIVE_PORT_0
static struct uart_fe310_data uart_fe310_data_0;
static struct uart_sifive_data uart_sifive_data_0;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_fe310_irq_cfg_func_0(void);
static void uart_sifive_irq_cfg_func_0(void);
#endif
static const struct uart_fe310_device_config uart_fe310_dev_cfg_0 = {
.port = CONFIG_FE310_UART_0_BASE_ADDR,
.sys_clk_freq = uart_fe310_port_0_clk_freq,
.baud_rate = CONFIG_FE310_UART_0_CURRENT_SPEED,
.rxcnt_irq = CONFIG_UART_FE310_PORT_0_RXCNT_IRQ,
.txcnt_irq = CONFIG_UART_FE310_PORT_0_TXCNT_IRQ,
static const struct uart_sifive_device_config uart_sifive_dev_cfg_0 = {
.port = CONFIG_SIFIVE_UART_0_BASE_ADDR,
.sys_clk_freq = uart_sifive_port_0_clk_freq,
.baud_rate = CONFIG_SIFIVE_UART_0_CURRENT_SPEED,
.rxcnt_irq = CONFIG_UART_SIFIVE_PORT_0_RXCNT_IRQ,
.txcnt_irq = CONFIG_UART_SIFIVE_PORT_0_TXCNT_IRQ,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.cfg_func = uart_fe310_irq_cfg_func_0,
.cfg_func = uart_sifive_irq_cfg_func_0,
#endif
};
DEVICE_AND_API_INIT(uart_fe310_0, CONFIG_FE310_UART_0_LABEL,
uart_fe310_init,
&uart_fe310_data_0, &uart_fe310_dev_cfg_0,
DEVICE_AND_API_INIT(uart_sifive_0, CONFIG_SIFIVE_UART_0_LABEL,
uart_sifive_init,
&uart_sifive_data_0, &uart_sifive_dev_cfg_0,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
(void *)&uart_fe310_driver_api);
(void *)&uart_sifive_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_fe310_irq_cfg_func_0(void)
static void uart_sifive_irq_cfg_func_0(void)
{
IRQ_CONNECT(CONFIG_FE310_UART_0_IRQ_0,
CONFIG_UART_FE310_PORT_0_IRQ_PRIORITY,
uart_fe310_irq_handler, DEVICE_GET(uart_fe310_0),
IRQ_CONNECT(CONFIG_SIFIVE_UART_0_IRQ_0,
CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY,
uart_sifive_irq_handler, DEVICE_GET(uart_sifive_0),
0);
irq_enable(CONFIG_FE310_UART_0_IRQ_0);
irq_enable(CONFIG_SIFIVE_UART_0_IRQ_0);
}
#endif
#endif /* CONFIG_UART_FE310_PORT_0 */
#endif /* CONFIG_UART_SIFIVE_PORT_0 */
#ifdef CONFIG_UART_FE310_PORT_1
#ifdef CONFIG_UART_SIFIVE_PORT_1
static struct uart_fe310_data uart_fe310_data_1;
static struct uart_sifive_data uart_sifive_data_1;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_fe310_irq_cfg_func_1(void);
static void uart_sifive_irq_cfg_func_1(void);
#endif
static const struct uart_fe310_device_config uart_fe310_dev_cfg_1 = {
.port = CONFIG_FE310_UART_1_BASE_ADDR,
.sys_clk_freq = uart_fe310_port_1_clk_freq,
.baud_rate = CONFIG_FE310_UART_1_CURRENT_SPEED,
.rxcnt_irq = CONFIG_UART_FE310_PORT_1_RXCNT_IRQ,
.txcnt_irq = CONFIG_UART_FE310_PORT_1_TXCNT_IRQ,
static const struct uart_sifive_device_config uart_sifive_dev_cfg_1 = {
.port = CONFIG_SIFIVE_UART_1_BASE_ADDR,
.sys_clk_freq = uart_sifive_port_1_clk_freq,
.baud_rate = CONFIG_SIFIVE_UART_1_CURRENT_SPEED,
.rxcnt_irq = CONFIG_UART_SIFIVE_PORT_1_RXCNT_IRQ,
.txcnt_irq = CONFIG_UART_SIFIVE_PORT_1_TXCNT_IRQ,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.cfg_func = uart_fe310_irq_cfg_func_1,
.cfg_func = uart_sifive_irq_cfg_func_1,
#endif
};
DEVICE_AND_API_INIT(uart_fe310_1, CONFIG_FE310_UART_1_LABEL,
uart_fe310_init,
&uart_fe310_data_1, &uart_fe310_dev_cfg_1,
DEVICE_AND_API_INIT(uart_sifive_1, CONFIG_SIFIVE_UART_1_LABEL,
uart_sifive_init,
&uart_sifive_data_1, &uart_sifive_dev_cfg_1,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
(void *)&uart_fe310_driver_api);
(void *)&uart_sifive_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_fe310_irq_cfg_func_1(void)
static void uart_sifive_irq_cfg_func_1(void)
{
IRQ_CONNECT(CONFIG_FE310_UART_1_IRQ_0,
CONFIG_UART_FE310_PORT_1_IRQ_PRIORITY,
uart_fe310_irq_handler, DEVICE_GET(uart_fe310_1),
IRQ_CONNECT(CONFIG_SIFIVE_UART_1_IRQ_0,
CONFIG_UART_SIFIVE_PORT_1_IRQ_PRIORITY,
uart_sifive_irq_handler, DEVICE_GET(uart_sifive_1),
0);
irq_enable(CONFIG_FE310_UART_1_IRQ_0);
irq_enable(CONFIG_SIFIVE_UART_1_IRQ_0);
}
#endif
#endif /* CONFIG_UART_FE310_PORT_1 */
#endif /* CONFIG_UART_SIFIVE_PORT_1 */