drivers: timer: add NXP LPTMR timer driver

Add NXP Kinetis Low Power Timer (LPTMR) OS timer driver shim. Since the
LPTMR does not support asynchronous changes to the timer period, only
non-tickless mode is supported.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>

drivers/timer/CMakeLists.txt

@@ -26,3 +26,4 @@ zephyr_sources_ifdef(CONFIG_NPCX_ITIM_TIMER npcx_itim_timer.c)
 zephyr_sources_ifdef(CONFIG_MCUX_OS_TIMER mcux_os_timer.c)
 zephyr_sources_ifdef(CONFIG_RCAR_CMT_TIMER rcar_cmt_timer.c)
 zephyr_sources_ifdef(CONFIG_APIC_TSC_DEADLINE_TIMER apic_tsc.c)
+zephyr_sources_ifdef(CONFIG_MCUX_LPTMR_TIMER mcux_lptmr_timer.c)

drivers/timer/Kconfig

@@ -406,4 +406,12 @@ config MCUX_OS_TIMER
 	  This module implements a kernel device driver for the NXP OS
 	  event timer and provides the standard "system clock driver" interfaces.
 
+config MCUX_LPTMR_TIMER
+	bool "MCUX LPTMR timer"
+	depends on HAS_MCUX_LPTMR && !COUNTER_MCUX_LPTMR
+	help
+	  This module implements a kernel device driver for the NXP MCUX Low
+	  Power Timer (LPTMR) and provides the standard "system clock driver"
+	  interfaces.
+
 endmenu

drivers/timer/mcux_lptmr_timer.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_kinetis_lptmr
+
+#include <drivers/timer/system_timer.h>
+#include <fsl_lptmr.h>
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "No LPTMR instance enabled in devicetree");
+
+/* Prescaler mapping */
+#define LPTMR_PRESCALER_2     kLPTMR_Prescale_Glitch_0
+#define LPTMR_PRESCALER_4     kLPTMR_Prescale_Glitch_1
+#define LPTMR_PRESCALER_8     kLPTMR_Prescale_Glitch_2
+#define LPTMR_PRESCALER_16    kLPTMR_Prescale_Glitch_3
+#define LPTMR_PRESCALER_32    kLPTMR_Prescale_Glitch_4
+#define LPTMR_PRESCALER_64    kLPTMR_Prescale_Glitch_5
+#define LPTMR_PRESCALER_128   kLPTMR_Prescale_Glitch_6
+#define LPTMR_PRESCALER_256   kLPTMR_Prescale_Glitch_7
+#define LPTMR_PRESCALER_512   kLPTMR_Prescale_Glitch_8
+#define LPTMR_PRESCALER_1024  kLPTMR_Prescale_Glitch_9
+#define LPTMR_PRESCALER_2048  kLPTMR_Prescale_Glitch_10
+#define LPTMR_PRESCALER_4096  kLPTMR_Prescale_Glitch_11
+#define LPTMR_PRESCALER_8192  kLPTMR_Prescale_Glitch_12
+#define LPTMR_PRESCALER_16384 kLPTMR_Prescale_Glitch_13
+#define LPTMR_PRESCALER_32768 kLPTMR_Prescale_Glitch_14
+#define LPTMR_PRESCALER_65536 kLPTMR_Prescale_Glitch_15
+#define TO_LPTMR_PRESCALER(val) _DO_CONCAT(LPTMR_PRESCALER_, val)
+
+/* Prescaler clock mapping */
+#define TO_LPTMR_CLK_SEL(val) _DO_CONCAT(kLPTMR_PrescalerClock_, val)
+
+/* Devicetree properties */
+#define LPTMR_BASE ((LPTMR_Type *)(DT_INST_REG_ADDR(0)))
+#define LPTMR_CLK_SOURCE TO_LPTMR_CLK_SEL(DT_INST_PROP(0, clk_source));
+#define LPTMR_PRESCALER TO_LPTMR_PRESCALER(DT_INST_PROP(0, prescaler));
+#define LPTMR_BYPASS_PRESCALER DT_INST_PROP(0, prescaler) == 1
+#define LPTMR_IRQN DT_INST_IRQN(0)
+#define LPTMR_IRQ_PRIORITY DT_INST_IRQ(0, priority)
+
+/* Timer cycles per tick */
+#define CYCLES_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
+			/ (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
+
+/* 32 bit cycle counter */
+static volatile uint32_t cycles;
+
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+	ARG_UNUSED(idle);
+
+	if (idle && (ticks == K_TICKS_FOREVER)) {
+		LPTMR_DisableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
+	}
+}
+
+void sys_clock_idle_exit(void)
+{
+	if (LPTMR_GetEnabledInterrupts(LPTMR_BASE) != kLPTMR_TimerInterruptEnable) {
+		LPTMR_EnableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
+	}
+}
+
+void sys_clock_disable(void)
+{
+	LPTMR_DisableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
+	LPTMR_StopTimer(LPTMR_BASE);
+}
+
+uint32_t sys_clock_elapsed(void)
+{
+	return 0;
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	return LPTMR_GetCurrentTimerCount(LPTMR_BASE) + cycles;
+}
+
+static void mcux_lptmr_timer_isr(void *arg)
+{
+	ARG_UNUSED(arg);
+
+	cycles += CYCLES_PER_TICK;
+
+	sys_clock_announce(1);
+	LPTMR_ClearStatusFlags(LPTMR_BASE, kLPTMR_TimerCompareFlag);
+}
+
+int sys_clock_driver_init(const struct device *dev)
+{
+	lptmr_config_t config;
+
+	ARG_UNUSED(dev);
+
+	LPTMR_GetDefaultConfig(&config);
+	config.timerMode = kLPTMR_TimerModeTimeCounter;
+	config.enableFreeRunning = false;
+	config.prescalerClockSource = LPTMR_CLK_SOURCE;
+
+#if LPTMR_BYPASS_PRESCALER
+	config.bypassPrescaler = true;
+#else /* LPTMR_BYPASS_PRESCALER */
+	config.bypassPrescaler = false;
+	config.value = LPTMR_PRESCALER;
+#endif /* !LPTMR_BYPASS_PRESCALER */
+
+	LPTMR_Init(LPTMR_BASE, &config);
+
+	IRQ_CONNECT(LPTMR_IRQN, LPTMR_IRQ_PRIORITY, mcux_lptmr_timer_isr, NULL, 0);
+	irq_enable(LPTMR_IRQN);
+
+	LPTMR_EnableInterrupts(LPTMR_BASE, kLPTMR_TimerInterruptEnable);
+	LPTMR_SetTimerPeriod(LPTMR_BASE, CYCLES_PER_TICK);
+	LPTMR_StartTimer(LPTMR_BASE);
+
+	return 0;
+}