From 2176ca9f9bdcf0028d185a6ac40bc8f672d9832d Mon Sep 17 00:00:00 2001 From: Damian Nikodem Date: Thu, 14 Mar 2024 12:08:07 +0100 Subject: [PATCH] intel_adsp: adsp_memory: update cAVS 2.5 memory definitions This commit updates the device tree and memory header file for the Intel cAVS 2.5 platform to define the LSBPM and HSBPM registers. Changes include: - Added node definitions for 'lsbpm' and 'hsbpm' in intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi - Updated adsp_memory.h Signed-off-by: Damian Nikodem --- dts/xtensa/intel/intel_adsp_cavs25.dtsi | 10 ++++++ dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi | 10 ++++++ .../cavs/include/cavs25/adsp_memory.h | 35 +++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/dts/xtensa/intel/intel_adsp_cavs25.dtsi b/dts/xtensa/intel/intel_adsp_cavs25.dtsi index 03faf222748..552d6cf9359 100644 --- a/dts/xtensa/intel/intel_adsp_cavs25.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs25.dtsi @@ -106,6 +106,16 @@ }; soc { + lsbpm: lsbpm@71d50 { + compatible = "intel,adsp-lsbpm"; + reg = <0x71d50 0x10>; + }; + + hsbpm: hsbpm@71d10 { + compatible = "intel,adsp-hsbpm"; + reg = <0x71d10 0x10>; + }; + shim: shim@71f00 { compatible = "intel,adsp-shim"; reg = <0x71f00 0x100>; diff --git a/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi b/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi index 28b982e993f..7ea35568fcd 100644 --- a/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi @@ -92,6 +92,16 @@ }; soc { + lsbpm: lsbpm@71d50 { + compatible = "intel,adsp-lsbpm"; + reg = <0x71d50 0x10>; + }; + + hsbpm: hsbpm@71d10 { + compatible = "intel,adsp-hsbpm"; + reg = <0x71d10 0x10>; + }; + shim: shim@71f00 { compatible = "intel,adsp-shim"; reg = <0x71f00 0x100>; diff --git a/soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h b/soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h index ed10a5d1367..231c254e7c8 100644 --- a/soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h +++ b/soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h @@ -65,5 +65,40 @@ /* The number of set associative cache way supported on L1 Instruction Cache */ #define ADSP_CxL1CCAP_ICMWC ((ADSP_CxL1CCAP_REG >> 20) & 7) +#ifndef _ASMLANGUAGE +/* L2 Local Memory Management */ + +struct cavs_hpsram_regs { + /** @brief power gating control */ + uint32_t HSxPGCTL; + /** @brief retention mode control */ + uint32_t HSxRMCTL; + /** @brief power gating status */ + uint32_t HSxPGISTS; +}; + +struct cavs_lpsram_regs { + /** @brief power gating control */ + uint32_t USxPGCTL; + /** @brief retention mode control */ + uint32_t USxRMCTL; + /** @brief power gating status */ + uint32_t USxPGISTS; +}; +#endif /* _ASMLANGUAGE */ + +/* These registers are for the L2 HP SRAM bank power management control and status.*/ +#define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm))) +#define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm))) + +#define HPSRAM_REGS(block_idx) ((volatile struct cavs_hpsram_regs *const) \ + (L2_HSBPM_BASE + L2_HSBPM_SIZE * (block_idx))) + +/* These registers are for the L2 LP SRAM bank power management control and status.*/ +#define L2_LSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(lsbpm))) +#define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm))) + +#define LPSRAM_REGS(block_idx) ((volatile struct cavs_lpsram_regs *const) \ + (L2_LSBPM_BASE + L2_LSBPM_SIZE * (block_idx))) #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */