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boards: nordic: nRF54L15DK: Add basic support for the L05 and L10 ICs

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The nRF54L05 and nRF54L10 are identical to the nRF54L15 except for their
memory sizes. Add support for emulating those ICs on the nRF54L15DK.
This commit only adds support for the main application core. Support for
the FLPR core may be added later.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This commit is contained in:
Carles Cufi 2024-11-06 18:42:45 +01:00 • committed by Henrik Brix Andersen
commit 21475774fc
21 changed files with 403 additions and 41 deletions
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6
boards/nordic/nrf54l15dk/Kconfig.defconfig
View file

@ -1,7 +1,8 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if BOARD_NRF54L15DK_NRF54L15_CPUAPP
if BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
BOARD_NRF54L15DK_NRF54L15_CPUAPP
config BT_CTLR
default BT
@ -9,4 +10,5 @@ config BT_CTLR
config ROM_START_OFFSET
default 0x800 if BOOTLOADER_MCUBOOT
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP
endif # BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
# BOARD_NRF54L15DK_NRF54L15_CPUAPP

2
boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk
View file

@ -2,6 +2,8 @@
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF54L15DK
select SOC_NRF54L05_CPUAPP if BOARD_NRF54L15DK_NRF54L05_CPUAPP
select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP
select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP
select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP

6
boards/nordic/nrf54l15dk/board.cmake
View file

@ -1,9 +1,11 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if(CONFIG_SOC_NRF54L15_CPUAPP)
if(CONFIG_SOC_NRF54L05_CPUAPP OR CONFIG_SOC_NRF54L10_CPUAPP OR
CONFIG_SOC_NRF54L15_CPUAPP)
board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR OR
CONFIG_SOC_NRF54L15_CPUFLPR)
board_runner_args(jlink "--speed=4000")
endif()

2
boards/nordic/nrf54l15dk/board.yml
View file

@ -3,6 +3,8 @@ board:
full_name: nRF54L15 DK
vendor: nordic
socs:
- name: nrf54l05
- name: nrf54l10
- name: nrf54l15
variants:
- name: xip

2
boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l15dk_nrf54l15-pinctrl.dtsi"
#include "nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi"
/ {
leds {

63
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.dts Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54l05_cpuapp.dtsi>
#include "nrf54l_05_10_15_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l15dk_nrf54l05-cpuapp";
model = "Nordic nRF54L15 DK nRF54L05 Application MCU";
chosen {
zephyr,code-partition = &slot0_partition;
zephyr,sram = &cpuapp_sram;
};
};
/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(96)>;
ranges = <0x0 0x20000000 DT_SIZE_K(96)>;
};
&cpuapp_rram {
reg = <0x0 DT_SIZE_K(500)>;
};
/* These partition sizes assume no FLPR area in RRAM */
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(100)>;
};
slot0_ns_partition: partition@29000 {
label = "image-0-nonsecure";
reg = <0x29000 DT_SIZE_K(100)>;
};
slot1_partition: partition@42000 {
label = "image-1";
reg = <0x42000 DT_SIZE_K(100)>;
};
slot1_ns_partition: partition@5b000 {
label = "image-1-nonsecure";
reg = <0x5b000 DT_SIZE_K(100)>;
};
storage_partition: partition@74000 {
label = "storage";
reg = <0x74000 DT_SIZE_K(36)>;
};
};
};

24
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.yaml Normal file
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@ -0,0 +1,24 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l15dk/nrf54l05/cpuapp
name: nRF54L15-DK-nRF54L05-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
sysbuild: true
ram: 96
flash: 100
supported:
- adc
- counter
- gpio
- i2c
- pwm
- retained_mem
- spi
- watchdog
- i2s

29
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp_defconfig Normal file
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@ -0,0 +1,29 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot
# be applied as the (0x0 - 0x400) is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable Cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Start SYSCOUNTER on driver init
CONFIG_NRF_GRTC_START_SYSCOUNTER=y

63
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54l10_cpuapp.dtsi>
#include "nrf54l_05_10_15_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l15dk_nrf54l10-cpuapp";
model = "Nordic nRF54L15 DK nRF54L10 Application MCU";
chosen {
zephyr,code-partition = &slot0_partition;
zephyr,sram = &cpuapp_sram;
};
};
/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(192)>;
ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
};
&cpuapp_rram {
reg = <0x0 DT_SIZE_K(1022)>;
};
/* These partition sizes assume no FLPR area in RRAM */
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(230)>;
};
slot0_ns_partition: partition@49800 {
label = "image-0-nonsecure";
reg = <0x49800 DT_SIZE_K(230)>;
};
slot1_partition: partition@83000 {
label = "image-1";
reg = <0x83000 DT_SIZE_K(230)>;
};
slot1_ns_partition: partition@bc800 {
label = "image-1-nonsecure";
reg = <0xbc800 DT_SIZE_K(230)>;
};
storage_partition: partition@f6000 {
label = "storage";
reg = <0xf6000 DT_SIZE_K(38)>;
};
};
};

24
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.yaml Normal file
View file

@ -0,0 +1,24 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l15dk/nrf54l10/cpuapp
name: nRF54L15-DK-nRF54L10-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
sysbuild: true
ram: 192
flash: 230
supported:
- adc
- counter
- gpio
- i2c
- pwm
- retained_mem
- spi
- watchdog
- i2s

29
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_defconfig Normal file
View file

@ -0,0 +1,29 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot
# be applied as the (0x0 - 0x400) is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable Cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Start SYSCOUNTER on driver init
CONFIG_NRF_GRTC_START_SYSCOUNTER=y

36
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts
View file

@ -6,7 +6,8 @@
/dts-v1/;
#include "nrf54l15_cpuapp_common.dtsi"
#include <nordic/nrf54l15_cpuapp.dtsi>
#include "nrf54l_05_10_15_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l15dk_nrf54l15-cpuapp";
@ -17,3 +18,36 @@
zephyr,sram = &cpuapp_sram;
};
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(324)>;
};
slot0_ns_partition: partition@61000 {
label = "image-0-nonsecure";
reg = <0x61000 DT_SIZE_K(324)>;
};
slot1_partition: partition@b2000 {
label = "image-1";
reg = <0xb2000 DT_SIZE_K(324)>;
};
slot1_ns_partition: partition@103000 {
label = "image-1-nonsecure";
reg = <0x103000 DT_SIZE_K(324)>;
};
/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
storage_partition: partition@15c000 {
label = "storage";
reg = <0x15c000 DT_SIZE_K(36)>;
};
};
};

0
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15-pinctrl.dtsi → boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi
View file

34
boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi → boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi
View file

@ -6,7 +6,6 @@
/* This file is common to the secure and non-secure domain */
#include <nordic/nrf54l15_cpuapp.dtsi>
#include "nrf54l15dk_common.dtsi"
/ {
@ -52,39 +51,6 @@
status = "okay";
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(324)>;
};
slot0_ns_partition: partition@61000 {
label = "image-0-nonsecure";
reg = <0x61000 DT_SIZE_K(324)>;
};
slot1_partition: partition@b2000 {
label = "image-1";
reg = <0xb2000 DT_SIZE_K(324)>;
};
slot1_ns_partition: partition@103000 {
label = "image-1-nonsecure";
reg = <0x103000 DT_SIZE_K(324)>;
};
/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
storage_partition: partition@15c000 {
label = "storage";
reg = <0x15c000 DT_SIZE_K(36)>;
};
};
};
&uart20 {
status = "okay";
};

8
samples/drivers/watchdog/boards/nrf54l15dk_nrf54l05_cpuapp.overlay Normal file
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@ -0,0 +1,8 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

8
samples/drivers/watchdog/boards/nrf54l15dk_nrf54l10_cpuapp.overlay Normal file
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@ -0,0 +1,8 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

43
tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l05_cpuapp.overlay Normal file
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@ -0,0 +1,43 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
/ {
zephyr,user {
io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
};
};
&adc {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
zephyr,input-positive = <NRF_SAADC_AIN1>;
zephyr,resolution = <10>;
};
channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1_4";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,input-positive = <NRF_SAADC_AIN4>;
zephyr,resolution = <12>;
};
channel@2 {
reg = <2>;
zephyr,gain = "ADC_GAIN_2_3";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
zephyr,input-positive = <NRF_SAADC_AIN2>;
zephyr,resolution = <10>;
};
};

43
tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l10_cpuapp.overlay Normal file
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@ -0,0 +1,43 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
/ {
zephyr,user {
io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
};
};
&adc {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
zephyr,input-positive = <NRF_SAADC_AIN1>;
zephyr,resolution = <10>;
};
channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1_4";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,input-positive = <NRF_SAADC_AIN4>;
zephyr,resolution = <12>;
};
channel@2 {
reg = <2>;
zephyr,gain = "ADC_GAIN_2_3";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
zephyr,input-positive = <NRF_SAADC_AIN2>;
zephyr,resolution = <10>;
};
};

9
tests/drivers/watchdog/wdt_basic_api/boards/nrf54l15dk_nrf54l05_cpuapp.overlay Normal file
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@ -0,0 +1,9 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

9
tests/drivers/watchdog/wdt_basic_api/boards/nrf54l15dk_nrf54l10_cpuapp.overlay Normal file
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@ -0,0 +1,9 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

4
tests/lib/cpp/cxx/testcase.yaml
View file

@ -34,9 +34,11 @@ tests:
# -std=c++98)
cpp.main.cpp98:
arch_exclude: posix
# Exclude nRF54L15, nRF54H20 and nRF9280 as Nordic HAL is not compatible with C++98.
# Exclude nRF54L series, nRF54H20 and nRF9280 as Nordic HAL is not compatible with C++98.
# Exclude CONFIG_HAS_RENESAS_RA_FSP as Renesas RA HAL is not compatible with C++98.
platform_exclude:
- nrf54l15dk/nrf54l05/cpuapp
- nrf54l15dk/nrf54l10/cpuapp
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l20pdk/nrf54l20/cpuapp
- nrf54h20dk/nrf54h20/cpuapp