michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: nuvoton: move init code from SYS_INIT to hooks

Browse source 
Replace SYS_INIT with SoC hooks and adapt SoC init code

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2024-09-10 09:42:40 -04:00 • committed by Henrik Brix Andersen
commit 21217309bf
9 changed files with 13 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

4
soc/nuvoton/npcm/npcm4/CMakeLists.txt
View file

@ -8,8 +8,4 @@ zephyr_include_directories(
${ZEPHYR_BASE}/drivers ${ZEPHYR_BASE}/drivers
) )
zephyr_sources(
soc.c
)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

20
soc/nuvoton/npcm/npcm4/soc.c
View file

@ -1,20 +0,0 @@
/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_npcm4_init(void)
{
return 0;
}
SYS_INIT(soc_npcm4_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

6
soc/nuvoton/npcx/common/scfg.c
View file

@ -143,7 +143,7 @@ void npcx_dbg_freeze_enable(bool enable)
} }
/* Pin-control driver registration */ /* Pin-control driver registration */
static int npcx_scfg_init(void) void scfg_init(void)
{ {
/* If booter doesn't set the host interface type */ /* If booter doesn't set the host interface type */
if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) { if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
@ -154,8 +154,4 @@ static int npcx_scfg_init(void)
for (int i = 0; i < ARRAY_SIZE(def_alts); i++) { for (int i = 0; i < ARRAY_SIZE(def_alts); i++) {
npcx_pinctrl_alt_sel(&def_alts[i], 0); npcx_pinctrl_alt_sel(&def_alts[i], 0);
} }
return 0;
} }
SYS_INIT(npcx_scfg_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

1
soc/nuvoton/npcx/npcx4/Kconfig
View file

@ -10,3 +10,4 @@ config SOC_SERIES_NPCX4
select CPU_HAS_FPU select CPU_HAS_FPU
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select HAS_PM select HAS_PM
select SOC_EARLY_INIT_HOOK

8
soc/nuvoton/npcx/npcx4/soc.c
View file

@ -18,7 +18,8 @@ static uintptr_t fiu_insts[] = {
DT_FOREACH_STATUS_OKAY(nuvoton_npcx_fiu_qspi, NPCX_FIU_INST_INIT) DT_FOREACH_STATUS_OKAY(nuvoton_npcx_fiu_qspi, NPCX_FIU_INST_INIT)
}; };
static int soc_npcx4_init(void) extern void scfg_init(void);
void soc_early_init_hook(void)
{ {
/* /*
* Make sure UMA_ADDR_SIZE field of UMA_ECTS register is zero in npcx4 * Make sure UMA_ADDR_SIZE field of UMA_ECTS register is zero in npcx4
@ -29,8 +30,5 @@ static int soc_npcx4_init(void)
SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0); SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
} }
scfg_init();
return 0;
} }
SYS_INIT(soc_npcx4_init, PRE_KERNEL_1, 0);

1
soc/nuvoton/npcx/npcx7/Kconfig
View file

@ -11,3 +11,4 @@ config SOC_SERIES_NPCX7
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select HAS_PM select HAS_PM
select SOC_EARLY_INIT_HOOK

8
soc/nuvoton/npcx/npcx7/soc.c
View file

@ -12,7 +12,8 @@
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_npcx7_init(void) extern void scfg_init(void);
void soc_early_init_hook(void)
{ {
struct scfg_reg *inst_scfg = (struct scfg_reg *) struct scfg_reg *inst_scfg = (struct scfg_reg *)
DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg); DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
@ -22,8 +23,5 @@ static int soc_npcx7_init(void)
* for more information. It will be fixed in next chip. * for more information. It will be fixed in next chip.
*/ */
inst_scfg->DEVCNT |= BIT(7); inst_scfg->DEVCNT |= BIT(7);
scfg_init();
return 0;
} }
SYS_INIT(soc_npcx7_init, PRE_KERNEL_1, 0);

1
soc/nuvoton/npcx/npcx9/Kconfig
View file

@ -11,6 +11,7 @@ config SOC_SERIES_NPCX9
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select SOC_FAMILY_NPCX select SOC_FAMILY_NPCX
select HAS_PM select HAS_PM
select SOC_EARLY_INIT_HOOK
config NPCX_VCC1_RST_HANG_WORKAROUND config NPCX_VCC1_RST_HANG_WORKAROUND
bool bool

8
soc/nuvoton/npcx/npcx9/soc.c
View file

@ -12,7 +12,8 @@
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_npcx9_init(void) extern void scfg_init(void);
void soc_early_init_hook(void)
{ {
if (IS_ENABLED(CONFIG_NPCX_VCC1_RST_HANG_WORKAROUND)) { if (IS_ENABLED(CONFIG_NPCX_VCC1_RST_HANG_WORKAROUND)) {
uintptr_t scfg_base = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg); uintptr_t scfg_base = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
@ -20,8 +21,5 @@ static int soc_npcx9_init(void)
SET_FIELD(NPCX_JEN_CTL1(scfg_base), NPCX_JEN_CTL1_JEN_HEN, SET_FIELD(NPCX_JEN_CTL1(scfg_base), NPCX_JEN_CTL1_JEN_HEN,
NPCX_JEN_CTL1_JEN_DISABLE); NPCX_JEN_CTL1_JEN_DISABLE);
} }
scfg_init();
return 0;
} }
SYS_INIT(soc_npcx9_init, PRE_KERNEL_1, 0);