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nordic: Update nrfx HAL function calls after switching to nrfx 2.0.0

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Calls to nrfx HAL functions in various nRF platform related source
files are complemented with pointers to relevant peripherals.

Additionally, TIMER HAL functions that got renamed in nrfx 2.0.0 are
updated in the qemu_cortex_m0 board supporting code.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2019-11-07 23:13:34 +01:00 • committed by Carles Cufí
commit 2115099932
6 changed files with 10 additions and 9 deletions
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3
boards/arm/nrf52840_pca10059/board.c
View file

@ -16,7 +16,8 @@ static int board_nrf52840_pca10059_init(struct device *dev)
* default and that is not enough to turn the green and blue LEDs on.
* Increase GPIO voltage to 3.0 volts.
*/
if ((nrf_power_mainregstatus_get() == NRF_POWER_MAINREGSTATUS_HIGH) &&
if ((nrf_power_mainregstatus_get(NRF_POWER) ==
NRF_POWER_MAINREGSTATUS_HIGH) &&
((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) ==
(UICR_REGOUT0_VOUT_DEFAULT << UICR_REGOUT0_VOUT_Pos))) {

6
boards/arm/qemu_cortex_m0/nrf_timer_timer.c
View file

@ -31,14 +31,14 @@ static u32_t counter_sub(u32_t a, u32_t b)
static void set_comparator(u32_t cyc)
{
nrf_timer_cc_write(TIMER, 0, cyc & COUNTER_MAX);
nrf_timer_cc_set(TIMER, 0, cyc & COUNTER_MAX);
}
static u32_t counter(void)
{
nrf_timer_task_trigger(TIMER, nrf_timer_capture_task_get(1));
return nrf_timer_cc_read(TIMER, 1);
return nrf_timer_cc_get(TIMER, 1);
}
void timer0_nrf_isr(void *arg)
@ -84,7 +84,7 @@ int z_clock_driver_init(struct device *device)
nrf_timer_frequency_set(TIMER, NRF_TIMER_FREQ_1MHz);
nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32);
nrf_timer_cc_write(TIMER, 0, CYC_PER_TICK);
nrf_timer_cc_set(TIMER, 0, CYC_PER_TICK);
nrf_timer_int_enable(TIMER, TIMER_INTENSET_COMPARE0_Msk);
/* Clear the event flag and possible pending interrupt */

2
soc/arm/nordic_nrf/nrf51/power.c
View file

@ -17,7 +17,7 @@ void sys_set_power_state(enum power_states state)
#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES
#ifdef CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_1
case SYS_POWER_STATE_DEEP_SLEEP_1:
nrf_power_system_off();
nrf_power_system_off(NRF_POWER);
break;
#endif
#endif

2
soc/arm/nordic_nrf/nrf51/soc.c
View file

@ -34,7 +34,7 @@ LOG_MODULE_REGISTER(soc);
Set general purpose retention register and reboot */
void sys_arch_reboot(int type)
{
nrf_power_gpregret_set((uint8_t)type);
nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
NVIC_SystemReset();
}

2
soc/arm/nordic_nrf/nrf52/power.c
View file

@ -17,7 +17,7 @@ void sys_set_power_state(enum power_states state)
#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES
#ifdef CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_1
case SYS_POWER_STATE_DEEP_SLEEP_1:
nrf_power_system_off();
nrf_power_system_off(NRF_POWER);
break;
#endif
#endif

4
soc/arm/nordic_nrf/nrf52/soc.c
View file

@ -45,7 +45,7 @@ LOG_MODULE_REGISTER(soc);
Set general purpose retention register and reboot */
void sys_arch_reboot(int type)
{
nrf_power_gpregret_set((uint8_t)type);
nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
NVIC_SystemReset();
}
@ -63,7 +63,7 @@ static int nordicsemi_nrf52_init(struct device *arg)
#endif
#if defined(CONFIG_SOC_DCDC_NRF52X)
nrf_power_dcdcen_set(true);
nrf_power_dcdcen_set(NRF_POWER, true);
#endif
/* Install default handler that simply resets the CPU