nordic: Update nrfx HAL function calls after switching to nrfx 2.0.0
Calls to nrfx HAL functions in various nRF platform related source files are complemented with pointers to relevant peripherals. Additionally, TIMER HAL functions that got renamed in nrfx 2.0.0 are updated in the qemu_cortex_m0 board supporting code. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
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2115099932
6 changed files with 10 additions and 9 deletions
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@ -16,7 +16,8 @@ static int board_nrf52840_pca10059_init(struct device *dev)
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* default and that is not enough to turn the green and blue LEDs on.
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* Increase GPIO voltage to 3.0 volts.
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*/
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if ((nrf_power_mainregstatus_get() == NRF_POWER_MAINREGSTATUS_HIGH) &&
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if ((nrf_power_mainregstatus_get(NRF_POWER) ==
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NRF_POWER_MAINREGSTATUS_HIGH) &&
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((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) ==
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(UICR_REGOUT0_VOUT_DEFAULT << UICR_REGOUT0_VOUT_Pos))) {
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@ -31,14 +31,14 @@ static u32_t counter_sub(u32_t a, u32_t b)
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static void set_comparator(u32_t cyc)
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{
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nrf_timer_cc_write(TIMER, 0, cyc & COUNTER_MAX);
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nrf_timer_cc_set(TIMER, 0, cyc & COUNTER_MAX);
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}
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static u32_t counter(void)
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{
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nrf_timer_task_trigger(TIMER, nrf_timer_capture_task_get(1));
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return nrf_timer_cc_read(TIMER, 1);
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return nrf_timer_cc_get(TIMER, 1);
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}
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void timer0_nrf_isr(void *arg)
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@ -84,7 +84,7 @@ int z_clock_driver_init(struct device *device)
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nrf_timer_frequency_set(TIMER, NRF_TIMER_FREQ_1MHz);
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nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32);
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nrf_timer_cc_write(TIMER, 0, CYC_PER_TICK);
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nrf_timer_cc_set(TIMER, 0, CYC_PER_TICK);
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nrf_timer_int_enable(TIMER, TIMER_INTENSET_COMPARE0_Msk);
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/* Clear the event flag and possible pending interrupt */
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@ -17,7 +17,7 @@ void sys_set_power_state(enum power_states state)
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES
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#ifdef CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_1
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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nrf_power_system_off();
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nrf_power_system_off(NRF_POWER);
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break;
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#endif
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#endif
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@ -34,7 +34,7 @@ LOG_MODULE_REGISTER(soc);
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Set general purpose retention register and reboot */
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void sys_arch_reboot(int type)
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{
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nrf_power_gpregret_set((uint8_t)type);
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nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
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NVIC_SystemReset();
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}
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@ -17,7 +17,7 @@ void sys_set_power_state(enum power_states state)
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#ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES
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#ifdef CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_1
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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nrf_power_system_off();
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nrf_power_system_off(NRF_POWER);
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break;
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#endif
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#endif
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@ -45,7 +45,7 @@ LOG_MODULE_REGISTER(soc);
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Set general purpose retention register and reboot */
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void sys_arch_reboot(int type)
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{
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nrf_power_gpregret_set((uint8_t)type);
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nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
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NVIC_SystemReset();
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}
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@ -63,7 +63,7 @@ static int nordicsemi_nrf52_init(struct device *arg)
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#endif
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#if defined(CONFIG_SOC_DCDC_NRF52X)
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nrf_power_dcdcen_set(true);
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nrf_power_dcdcen_set(NRF_POWER, true);
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#endif
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/* Install default handler that simply resets the CPU
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