diff --git a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h index 1f17fe090ff..57db24e4d44 100644 --- a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h +++ b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h @@ -3,59 +3,14 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_H_ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_H_ -#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ - defined(CONFIG_CPU_CORTEX_M3) || \ - defined(CONFIG_CPU_CORTEX_M4) || \ - defined(CONFIG_CPU_CORTEX_M7) -#include -#elif defined(CONFIG_CPU_CORTEX_M23) || \ - defined(CONFIG_CPU_CORTEX_M33) || \ - defined(CONFIG_CPU_CORTEX_M55) -#include -#else -#error "Unsupported ARM CPU" +#ifndef CONFIG_COMPAT_INCLUDES +#warning "This header file has moved, include instead." #endif -#ifndef _ASMLANGUAGE - -/* Region definition data structure */ -struct arm_mpu_region { - /* Region Base Address */ - uint32_t base; - /* Region Name */ - const char *name; - /* Region Attributes */ - arm_mpu_region_attr_t attr; -}; - -/* MPU configuration data structure */ -struct arm_mpu_config { - /* Number of regions */ - uint32_t num_regions; - /* Regions */ - const struct arm_mpu_region *mpu_regions; -}; - -#define MPU_REGION_ENTRY(_name, _base, _attr) \ - {\ - .name = _name, \ - .base = _base, \ - .attr = _attr, \ - } - -/* Reference to the MPU configuration. - * - * This struct is defined and populated for each SoC (in the SoC definition), - * and holds the build-time configuration information for the fixed MPU - * regions enabled during kernel initialization. Dynamic MPU regions (e.g. - * for Thread Stack, Stack Guards, etc.) are programmed during runtime, thus, - * not kept here. - */ -extern const struct arm_mpu_config mpu_config; - -#endif /* _ASMLANGUAGE */ +#include #endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_H_ */ diff --git a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h index 50cacb8f95f..c9a466dfaad 100644 --- a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h +++ b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h @@ -5,274 +5,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _ASMLANGUAGE +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_V7M_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_V7M_H_ -#include - -/* Convenience macros to represent the ARMv7-M-specific - * configuration for memory access permission and - * cache-ability attribution. - */ - -/* Privileged No Access, Unprivileged No Access */ -#define NO_ACCESS 0x0 -#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged No Access, Unprivileged No Access */ -#define P_NA_U_NA 0x0 -#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged No Access */ -#define P_RW_U_NA 0x1 -#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Only */ -#define P_RW_U_RO 0x2 -#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Write */ -#define P_RW_U_RW 0x3U -#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Write */ -#define FULL_ACCESS 0x3 -#define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Only, Unprivileged No Access */ -#define P_RO_U_NA 0x5 -#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Only, Unprivileged Read Only */ -#define P_RO_U_RO 0x6 -#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) -/* Privileged Read Only, Unprivileged Read Only */ -#define RO 0x7 -#define RO_Msk ((RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) - -/* Attribute flag for not-allowing execution (eXecute Never) */ -#define NOT_EXEC MPU_RASR_XN_Msk - -/* The following definitions are for internal use in arm_mpu.h. */ -#define STRONGLY_ORDERED_SHAREABLE MPU_RASR_S_Msk -#define DEVICE_SHAREABLE (MPU_RASR_B_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE \ - (MPU_RASR_C_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE MPU_RASR_C_Msk -#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE \ - (MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE \ - (MPU_RASR_C_Msk | MPU_RASR_B_Msk) -#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE \ - ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE \ - (1 << MPU_RASR_TEX_Pos) -#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE \ - ((1 << MPU_RASR_TEX_Pos) |\ - MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) -#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE \ - ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk) -#define DEVICE_NON_SHAREABLE (2 << MPU_RASR_TEX_Pos) - -/* Bit-masks to disable sub-regions. */ -#define SUB_REGION_0_DISABLED ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_1_DISABLED ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_2_DISABLED ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_3_DISABLED ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_4_DISABLED ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_5_DISABLED ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_6_DISABLED ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) -#define SUB_REGION_7_DISABLED ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) - - -#define REGION_SIZE(size) ((ARM_MPU_REGION_SIZE_ ## size \ - << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - -#define REGION_32B REGION_SIZE(32B) -#define REGION_64B REGION_SIZE(64B) -#define REGION_128B REGION_SIZE(128B) -#define REGION_256B REGION_SIZE(256B) -#define REGION_512B REGION_SIZE(512B) -#define REGION_1K REGION_SIZE(1KB) -#define REGION_2K REGION_SIZE(2KB) -#define REGION_4K REGION_SIZE(4KB) -#define REGION_8K REGION_SIZE(8KB) -#define REGION_16K REGION_SIZE(16KB) -#define REGION_32K REGION_SIZE(32KB) -#define REGION_64K REGION_SIZE(64KB) -#define REGION_128K REGION_SIZE(128KB) -#define REGION_256K REGION_SIZE(256KB) -#define REGION_512K REGION_SIZE(512KB) -#define REGION_1M REGION_SIZE(1MB) -#define REGION_2M REGION_SIZE(2MB) -#define REGION_4M REGION_SIZE(4MB) -#define REGION_8M REGION_SIZE(8MB) -#define REGION_16M REGION_SIZE(16MB) -#define REGION_32M REGION_SIZE(32MB) -#define REGION_64M REGION_SIZE(64MB) -#define REGION_128M REGION_SIZE(128MB) -#define REGION_256M REGION_SIZE(256MB) -#define REGION_512M REGION_SIZE(512MB) -#define REGION_1G REGION_SIZE(1GB) -#define REGION_2G REGION_SIZE(2GB) -#define REGION_4G REGION_SIZE(4GB) - -/* Some helper defines for common regions */ -#define REGION_RAM_ATTR(size) \ -{ \ - (NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \ - MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ -} -#define REGION_RAM_NOCACHE_ATTR(size) \ -{ \ - (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ - MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ -} -#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) -#define REGION_FLASH_ATTR(size) \ -{ \ - (NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | \ - P_RW_U_RO_Msk) \ -} -#else -#define REGION_FLASH_ATTR(size) \ -{ \ - (NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | RO_Msk) \ -} +#ifndef CONFIG_COMPAT_INCLUDES +#warning "This header file has moved, include instead." #endif -#define REGION_PPB_ATTR(size) { (STRONGLY_ORDERED_SHAREABLE | size | \ - P_RW_U_NA_Msk) } -#define REGION_IO_ATTR(size) { (DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk) } -struct arm_mpu_region_attr { - /* Attributes belonging to RASR (including the encoded region size) */ - uint32_t rasr; -}; +#include -typedef struct arm_mpu_region_attr arm_mpu_region_attr_t; - -/* Typedef for the k_mem_partition attribute */ -typedef struct { - uint32_t rasr_attr; -} k_mem_partition_attr_t; - -/* Read-Write access permission attributes */ -#define _K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS_Msk | NOT_EXEC) -#define _K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW_Msk | NOT_EXEC) -#define _K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO_Msk | NOT_EXEC) -#define _K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA_Msk | NOT_EXEC) -#define _K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO_Msk | NOT_EXEC) -#define _K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA_Msk | NOT_EXEC) - -/* Execution-allowed attributes */ -#define _K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW_Msk) -#define _K_MEM_PARTITION_P_RWX_U_RX (P_RW_U_RO_Msk) -#define _K_MEM_PARTITION_P_RX_U_RX (P_RO_U_RO_Msk) - -/* Kernel macros for memory attribution - * (access permissions and cache-ability). - * - * The macros are to be stored in k_mem_partition_attr_t - * objects. The format of k_mem_partition_attr_t is an - * "1-1" mapping of the ARMv7-M MPU RASR attribute register - * fields (excluding the and bit-fields). - */ - -/* Read-Write access permission attributes (default cache-ability) */ -#define K_MEM_PARTITION_P_NA_U_NA ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_NA_U_NA | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RW_U_RW | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RW_U_RO ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RW_U_RO | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RW_U_NA | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RO_U_RO | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RO_U_NA | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) - -/* Execution-allowed attributes (default-cacheability) */ -#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RWX_U_RWX | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RWX_U_RX ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RWX_U_RX | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) -#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \ - { _K_MEM_PARTITION_P_RX_U_RX | \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) - -/* - * @brief Evaluate Write-ability - * - * Evaluate whether the access permissions include write-ability. - * - * @param attr The k_mem_partition_attr_t object holding the - * MPU attributes to be checked against write-ability. - */ -#define K_MEM_PARTITION_IS_WRITABLE(attr) \ - ({ \ - int __is_writable__; \ - switch (attr.rasr_attr & MPU_RASR_AP_Msk) { \ - case P_RW_U_RW_Msk: \ - case P_RW_U_RO_Msk: \ - case P_RW_U_NA_Msk: \ - __is_writable__ = 1; \ - break; \ - default: \ - __is_writable__ = 0; \ - } \ - __is_writable__; \ - }) - -/* - * @brief Evaluate Execution allowance - * - * Evaluate whether the access permissions include execution. - * - * @param attr The k_mem_partition_attr_t object holding the - * MPU attributes to be checked against execution - * allowance. - */ -#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ - (!((attr.rasr_attr) & (NOT_EXEC))) - -/* Attributes for no-cache enabling (share-ability is selected by default) */ - -#define K_MEM_PARTITION_P_NA_U_NA_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_NA_U_NA \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RW_U_RW \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RW_U_RO_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RW_U_RO \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RW_U_NA \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RO_U_RO \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RO_U_NA \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) - -#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RWX_U_RWX \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RWX_U_RX_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RWX_U_RX \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) -#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE ((k_mem_partition_attr_t) \ - {(_K_MEM_PARTITION_P_RX_U_RX \ - | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) - -#endif /* _ASMLANGUAGE */ - -#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ - BUILD_ASSERT(!(((size) & ((size) - 1))) && \ - (size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \ - !((uint32_t)(start) & ((size) - 1)), \ - "the size of the partition must be power of 2" \ - " and greater than or equal to the minimum MPU region size." \ - "start address of the partition must align with size.") +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_V7M_H_ */ diff --git a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h index c4535699f0f..fa1b3cd588d 100644 --- a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h +++ b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h @@ -5,255 +5,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _ASMLANGUAGE +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_V8M_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_V8M_H_ -#include +#ifndef CONFIG_COMPAT_INCLUDES +#warning "This header file has moved, include instead." +#endif -/* Convenience macros to represent the ARMv8-M-specific - * configuration for memory access permission and - * cache-ability attribution. - */ +#include -/* Privileged No Access, Unprivileged No Access */ -/*#define NO_ACCESS 0x0 */ -/*#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */ -/* Privileged No Access, Unprivileged No Access */ -/*#define P_NA_U_NA 0x0 */ -/*#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */ -/* Privileged Read Write, Unprivileged No Access */ -#define P_RW_U_NA 0x0 -#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Only */ -/*#define P_RW_U_RO 0x2 */ -/*#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)*/ -/* Privileged Read Write, Unprivileged Read Write */ -#define P_RW_U_RW 0x1 -#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) -/* Privileged Read Write, Unprivileged Read Write */ -#define FULL_ACCESS 0x1 -#define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) -/* Privileged Read Only, Unprivileged No Access */ -#define P_RO_U_NA 0x2 -#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) -/* Privileged Read Only, Unprivileged Read Only */ -#define P_RO_U_RO 0x3 -#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) -/* Privileged Read Only, Unprivileged Read Only */ -#define RO 0x3 -#define RO_Msk ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) - -/* Attribute flag for not-allowing execution (eXecute Never) */ -#define NOT_EXEC MPU_RBAR_XN_Msk - -/* Attribute flags for share-ability */ -#define NON_SHAREABLE 0x0 -#define NON_SHAREABLE_Msk \ - ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) -#define OUTER_SHAREABLE 0x2 -#define OUTER_SHAREABLE_Msk \ - ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) -#define INNER_SHAREABLE 0x3 -#define INNER_SHAREABLE_Msk \ - ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) - -/* Helper define to calculate the region limit address. */ -#define REGION_LIMIT_ADDR(base, size) \ - (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk) - - -/* Attribute flags for cache-ability */ - -/* Read/Write Allocation Configurations for Cacheable Memory */ -#define R_NON_W_NON 0x0 /* Do not allocate Read/Write */ -#define R_NON_W_ALLOC 0x1 /* Do not allocate Read, Allocate Write */ -#define R_ALLOC_W_NON 0x2 /* Allocate Read, Do not allocate Write */ -#define R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */ - -/* Memory Attributes for Normal Memory */ -#define NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */ -#define NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */ -#define NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable */ - -#define NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */ -#define NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */ -#define NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable */ - -#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS \ - ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) \ - | \ - (NORMAL_I_WT_NT | R_ALLOC_W_NON)) \ - -#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS \ - ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) \ - | \ - (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC)) - -#define NORMAL_OUTER_INNER_NON_CACHEABLE \ - ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) \ - | \ - (NORMAL_I_NON_C | R_NON_W_NON)) - -/* Common cache-ability configuration for Flash, SRAM regions */ -#define MPU_CACHE_ATTRIBUTES_FLASH \ - NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS -#define MPU_CACHE_ATTRIBUTES_SRAM \ - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS -#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE \ - NORMAL_OUTER_INNER_NON_CACHEABLE - -/* Global MAIR configurations */ -#define MPU_MAIR_ATTR_FLASH MPU_CACHE_ATTRIBUTES_FLASH -#define MPU_MAIR_INDEX_FLASH 0 -#define MPU_MAIR_ATTR_SRAM MPU_CACHE_ATTRIBUTES_SRAM -#define MPU_MAIR_INDEX_SRAM 1 -#define MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE -#define MPU_MAIR_INDEX_SRAM_NOCACHE 2 - -/* Some helper defines for common regions. - * - * Note that the ARMv8-M MPU architecture requires that the - * enabled MPU regions are non-overlapping. Therefore, it is - * recommended to use these helper defines only for configuring - * fixed MPU regions at build-time (i.e. regions that are not - * expected to be re-programmed or re-adjusted at run-time so - * that they do not overlap with other MPU regions). - */ -#define REGION_RAM_ATTR(base, size) \ - {\ - .rbar = NOT_EXEC | \ - P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ - } - -#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) -/* Note that the access permissions allow for un-privileged writes, contrary - * to ARMv7-M where un-privileged code has Read-Only permissions. - */ -#define REGION_FLASH_ATTR(base, size) \ - {\ - .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_FLASH, \ - .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ - } -#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */ -#define REGION_FLASH_ATTR(base, size) \ - {\ - .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_FLASH, \ - .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ - } -#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */ - - -struct arm_mpu_region_attr { - /* Attributes belonging to RBAR */ - uint8_t rbar: 5; - /* MAIR index for attribute indirection */ - uint8_t mair_idx: 3; - /* Region Limit Address value to be written to the RLAR register. */ - uint32_t r_limit; -}; - -typedef struct arm_mpu_region_attr arm_mpu_region_attr_t; - -/* Typedef for the k_mem_partition attribute */ -typedef struct { - uint16_t rbar; - uint16_t mair_idx; -} k_mem_partition_attr_t; - -/* Kernel macros for memory attribution - * (access permissions and cache-ability). - * - * The macros are to be stored in k_mem_partition_attr_t - * objects. The format of a k_mem_partition_attr_t object - * is as follows: field contains a direct mapping - * of the and bit-fields of the RBAR register; - * field contains a direct mapping of AttrIdx - * bit-field, stored in RLAR register. - */ - -/* Read-Write access permission attributes */ -#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \ - {(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) -#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \ - {(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) -#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \ - {(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) -#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \ - {(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) - -/* Execution-allowed attributes */ -#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \ - {(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM}) -#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \ - {(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM}) - -/* - * @brief Evaluate Write-ability - * - * Evaluate whether the access permissions include write-ability. - * - * @param attr The k_mem_partition_attr_t object holding the - * MPU attributes to be checked against write-ability. - */ -#define K_MEM_PARTITION_IS_WRITABLE(attr) \ - ({ \ - int __is_writable__; \ - switch (attr.rbar & MPU_RBAR_AP_Msk) { \ - case P_RW_U_RW_Msk: \ - case P_RW_U_NA_Msk: \ - __is_writable__ = 1; \ - break; \ - default: \ - __is_writable__ = 0; \ - } \ - __is_writable__; \ - }) - -/* - * @brief Evaluate Execution allowance - * - * Evaluate whether the access permissions include execution. - * - * @param attr The k_mem_partition_attr_t object holding the - * MPU attributes to be checked against execution - * allowance. - */ -#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ - (!((attr.rbar) & (NOT_EXEC))) - -/* Attributes for no-cache enabling (share-ability is selected by default) */ - -/* Read-Write access permission attributes */ -#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE ((k_mem_partition_attr_t) \ - {(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ - MPU_MAIR_INDEX_SRAM_NOCACHE}) -#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE ((k_mem_partition_attr_t) \ - {(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ - MPU_MAIR_INDEX_SRAM_NOCACHE}) -#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE ((k_mem_partition_attr_t) \ - {(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ - MPU_MAIR_INDEX_SRAM_NOCACHE}) -#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE ((k_mem_partition_attr_t) \ - {(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ - MPU_MAIR_INDEX_SRAM_NOCACHE}) - -/* Execution-allowed attributes */ -#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE ((k_mem_partition_attr_t) \ - {(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk), MPU_MAIR_INDEX_SRAM_NOCACHE}) -#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE ((k_mem_partition_attr_t) \ - {(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk), MPU_MAIR_INDEX_SRAM_NOCACHE}) - -#endif /* _ASMLANGUAGE */ - -#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ - BUILD_ASSERT((size > 0) && ((uint32_t)start % \ - CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \ - ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \ - " the start and size of the partition must align " \ - "with the minimum MPU region size.") +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_MPU_V8M_H_ */ diff --git a/include/arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h b/include/arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h index b9baf723e53..f17032fb87d 100644 --- a/include/arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h +++ b/include/arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h @@ -3,271 +3,14 @@ * * SPDX-License-Identifier: Apache-2.0 */ + #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_NXP_MPU_H_ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_NXP_MPU_H_ -#ifndef _ASMLANGUAGE - -#include - -#define NXP_MPU_BASE SYSMPU_BASE - -#define NXP_MPU_REGION_NUMBER 12 - -/* Bus Master User Mode Access */ -#define UM_READ 4 -#define UM_WRITE 2 -#define UM_EXEC 1 - -#define BM0_UM_SHIFT 0 -#define BM1_UM_SHIFT 6 -#define BM2_UM_SHIFT 12 -#define BM3_UM_SHIFT 18 - -/* Bus Master Supervisor Mode Access */ -#define SM_RWX_ALLOW 0 -#define SM_RX_ALLOW 1 -#define SM_RW_ALLOW 2 -#define SM_SAME_AS_UM 3 - -#define BM0_SM_SHIFT 3 -#define BM1_SM_SHIFT 9 -#define BM2_SM_SHIFT 15 -#define BM3_SM_SHIFT 21 - -#define BM4_WE_SHIFT 24 -#define BM4_RE_SHIFT 25 - -#ifdef CONFIG_USB_KINETIS -#define BM4_PERMISSIONS ((1 << BM4_RE_SHIFT) | (1 << BM4_WE_SHIFT)) -#else -#define BM4_PERMISSIONS 0 +#ifndef CONFIG_COMPAT_INCLUDES +#warning "This header file has moved, include instead." #endif -/* Read Attribute */ -#define MPU_REGION_READ ((UM_READ << BM0_UM_SHIFT) | \ - (UM_READ << BM1_UM_SHIFT) | \ - (UM_READ << BM2_UM_SHIFT) | \ - (UM_READ << BM3_UM_SHIFT)) - -/* Write Attribute */ -#define MPU_REGION_WRITE ((UM_WRITE << BM0_UM_SHIFT) | \ - (UM_WRITE << BM1_UM_SHIFT) | \ - (UM_WRITE << BM2_UM_SHIFT) | \ - (UM_WRITE << BM3_UM_SHIFT)) - -/* Execute Attribute */ -#define MPU_REGION_EXEC ((UM_EXEC << BM0_UM_SHIFT) | \ - (UM_EXEC << BM1_UM_SHIFT) | \ - (UM_EXEC << BM2_UM_SHIFT) | \ - (UM_EXEC << BM3_UM_SHIFT)) - -/* Super User Attributes */ -#define MPU_REGION_SU ((SM_SAME_AS_UM << BM0_SM_SHIFT) | \ - (SM_SAME_AS_UM << BM1_SM_SHIFT) | \ - (SM_SAME_AS_UM << BM2_SM_SHIFT) | \ - (SM_SAME_AS_UM << BM3_SM_SHIFT)) - -#define MPU_REGION_SU_RX ((SM_RX_ALLOW << BM0_SM_SHIFT) | \ - (SM_RX_ALLOW << BM1_SM_SHIFT) | \ - (SM_RX_ALLOW << BM2_SM_SHIFT) | \ - (SM_RX_ALLOW << BM3_SM_SHIFT)) - -#define MPU_REGION_SU_RW ((SM_RW_ALLOW << BM0_SM_SHIFT) | \ - (SM_RW_ALLOW << BM1_SM_SHIFT) | \ - (SM_RW_ALLOW << BM2_SM_SHIFT) | \ - (SM_RW_ALLOW << BM3_SM_SHIFT)) - -#define MPU_REGION_SU_RWX ((SM_RWX_ALLOW << BM0_SM_SHIFT) | \ - (SM_RWX_ALLOW << BM1_SM_SHIFT) | \ - (SM_RWX_ALLOW << BM2_SM_SHIFT) | \ - (SM_RWX_ALLOW << BM3_SM_SHIFT)) - -/* The ENDADDR field has the last 5 bit reserved and set to 1 */ -#define ENDADDR_ROUND(x) (x - 0x1F) - -#define REGION_USER_MODE_ATTR {(MPU_REGION_READ | \ - MPU_REGION_WRITE | \ - MPU_REGION_SU)} - -/* Some helper defines for common regions */ -#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) -#define REGION_RAM_ATTR {((MPU_REGION_SU_RWX) | \ - ((UM_READ | UM_WRITE | UM_EXEC) << BM3_UM_SHIFT) | \ - (BM4_PERMISSIONS))} - -#define REGION_FLASH_ATTR {(MPU_REGION_SU_RWX)} - -#else -#define REGION_RAM_ATTR {((MPU_REGION_SU_RW) | \ - ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | \ - (BM4_PERMISSIONS))} - -#define REGION_FLASH_ATTR {(MPU_REGION_READ | \ - MPU_REGION_EXEC | \ - MPU_REGION_SU)} -#endif - -#define REGION_IO_ATTR {(MPU_REGION_READ | \ - MPU_REGION_WRITE | \ - MPU_REGION_EXEC | \ - MPU_REGION_SU)} - -#define REGION_RO_ATTR {(MPU_REGION_READ | MPU_REGION_SU)} - -#define REGION_USER_RO_ATTR {(MPU_REGION_READ | \ - MPU_REGION_SU)} - -/* ENET (Master 3) and USB (Master 4) devices will not be able -to access RAM when the region is dynamically disabled in NXP MPU. -DEBUGGER (Master 1) can't be disabled in Region 0. */ -#define REGION_DEBUGGER_AND_DEVICE_ATTR {((MPU_REGION_SU) | \ - ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | \ - (BM4_PERMISSIONS))} - -#define REGION_DEBUG_ATTR {MPU_REGION_SU} - -#define REGION_BACKGROUND_ATTR {MPU_REGION_SU_RW} - -struct nxp_mpu_region_attr { - /* NXP MPU region access permission attributes */ - uint32_t attr; -}; - -typedef struct nxp_mpu_region_attr nxp_mpu_region_attr_t; - -/* Typedef for the k_mem_partition attribute*/ -typedef struct { - uint32_t ap_attr; -} k_mem_partition_attr_t; - -/* Kernel macros for memory attribution - * (access permissions and cache-ability). - * - * The macros are to be stored in k_mem_partition_attr_t - * objects. - */ - -/* Read-Write access permission attributes */ -#define K_MEM_PARTITION_P_NA_U_NA ((k_mem_partition_attr_t) \ - {(MPU_REGION_SU)}) -#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \ - {(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)}) -#define K_MEM_PARTITION_P_RW_U_RO ((k_mem_partition_attr_t) \ - {(MPU_REGION_READ | MPU_REGION_SU_RW)}) -#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \ - {(MPU_REGION_SU_RW)}) -#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \ - {(MPU_REGION_READ | MPU_REGION_SU)}) -#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \ - {(MPU_REGION_SU_RX)}) - -/* Execution-allowed attributes */ -#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \ - {(MPU_REGION_READ | MPU_REGION_WRITE | \ - MPU_REGION_EXEC | MPU_REGION_SU)}) -#define K_MEM_PARTITION_P_RWX_U_RX ((k_mem_partition_attr_t) \ - {(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU_RWX)}) -#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \ - {(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)}) - -/* - * @brief Evaluate Write-ability - * - * Evaluate whether the access permissions include write-ability. - * - * @param attr The k_mem_partition_attr_t object holding the - * MPU attributes to be checked against write-ability. - */ -#define K_MEM_PARTITION_IS_WRITABLE(attr) \ - ({ \ - int __is_writable__; \ - switch (attr.ap_attr) { \ - case MPU_REGION_WRITE: \ - case MPU_REGION_SU_RW: \ - __is_writable__ = 1; \ - break; \ - default: \ - __is_writable__ = 0; \ - } \ - __is_writable__; \ - }) - -/* - * @brief Evaluate Execution allowance - * - * Evaluate whether the access permissions include execution. - * - * @param attr The k_mem_partition_attr_t object holding the - * MPU attributes to be checked against execution - * allowance. - */ -#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ - ({ \ - int __is_executable__; \ - switch (attr.ap_attr) { \ - case MPU_REGION_SU_RX: \ - case MPU_REGION_EXEC: \ - __is_executable__ = 1; \ - break; \ - default: \ - __is_executable__ = 0; \ - } \ - __is_executable__; \ - }) - - -/* Region definition data structure */ -struct nxp_mpu_region { - /* Region Base Address */ - uint32_t base; - /* Region End Address */ - uint32_t end; - /* Region Name */ - const char *name; - /* Region Attributes */ - nxp_mpu_region_attr_t attr; -}; - -#define MPU_REGION_ENTRY(_name, _base, _end, _attr) \ - {\ - .name = _name, \ - .base = _base, \ - .end = _end, \ - .attr = _attr, \ - } - -/* MPU configuration data structure */ -struct nxp_mpu_config { - /* Number of regions */ - uint32_t num_regions; - /* Regions */ - const struct nxp_mpu_region *mpu_regions; - /* SRAM Region */ - uint32_t sram_region; -}; - -/* Reference to the MPU configuration. - * - * This struct is defined and populated for each SoC (in the SoC definition), - * and holds the build-time configuration information for the fixed MPU - * regions enabled during kernel initialization. Dynamic MPU regions (e.g. - * for Thread Stack, Stack Guards, etc.) are programmed during runtime, thus, - * not kept here. - */ -extern const struct nxp_mpu_config mpu_config; - -#endif /* _ASMLANGUAGE */ - -#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ - BUILD_ASSERT((size) % \ - CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0 && \ - (size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \ - (uint32_t)(start) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0, \ - "the size of the partition must align with minimum MPU \ - region size" \ - " and greater than or equal to minimum MPU region size." \ - "start address of the partition must align with minimum MPU \ - region size.") +#include #endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_NXP_MPU_H_ */ diff --git a/include/arch/arm/aarch32/mpu/arm_mpu.h b/include/arch/arm/aarch32/mpu/arm_mpu.h new file mode 100644 index 00000000000..413d669d08c --- /dev/null +++ b/include/arch/arm/aarch32/mpu/arm_mpu.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_MPU_ARM_MPU_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_MPU_ARM_MPU_H_ + +#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ + defined(CONFIG_CPU_CORTEX_M3) || \ + defined(CONFIG_CPU_CORTEX_M4) || \ + defined(CONFIG_CPU_CORTEX_M7) +#include +#elif defined(CONFIG_CPU_CORTEX_M23) || \ + defined(CONFIG_CPU_CORTEX_M33) || \ + defined(CONFIG_CPU_CORTEX_M55) +#include +#else +#error "Unsupported ARM CPU" +#endif + +#ifndef _ASMLANGUAGE + +/* Region definition data structure */ +struct arm_mpu_region { + /* Region Base Address */ + uint32_t base; + /* Region Name */ + const char *name; + /* Region Attributes */ + arm_mpu_region_attr_t attr; +}; + +/* MPU configuration data structure */ +struct arm_mpu_config { + /* Number of regions */ + uint32_t num_regions; + /* Regions */ + const struct arm_mpu_region *mpu_regions; +}; + +#define MPU_REGION_ENTRY(_name, _base, _attr) \ + {\ + .name = _name, \ + .base = _base, \ + .attr = _attr, \ + } + +/* Reference to the MPU configuration. + * + * This struct is defined and populated for each SoC (in the SoC definition), + * and holds the build-time configuration information for the fixed MPU + * regions enabled during kernel initialization. Dynamic MPU regions (e.g. + * for Thread Stack, Stack Guards, etc.) are programmed during runtime, thus, + * not kept here. + */ +extern const struct arm_mpu_config mpu_config; + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_MPU_ARM_MPU_H_ */ diff --git a/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h b/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h new file mode 100644 index 00000000000..50cacb8f95f --- /dev/null +++ b/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2018 Linaro Limited. + * Copyright (c) 2018 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ASMLANGUAGE + +#include + +/* Convenience macros to represent the ARMv7-M-specific + * configuration for memory access permission and + * cache-ability attribution. + */ + +/* Privileged No Access, Unprivileged No Access */ +#define NO_ACCESS 0x0 +#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged No Access, Unprivileged No Access */ +#define P_NA_U_NA 0x0 +#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged No Access */ +#define P_RW_U_NA 0x1 +#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Only */ +#define P_RW_U_RO 0x2 +#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Write */ +#define P_RW_U_RW 0x3U +#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Write */ +#define FULL_ACCESS 0x3 +#define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Only, Unprivileged No Access */ +#define P_RO_U_NA 0x5 +#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Only, Unprivileged Read Only */ +#define P_RO_U_RO 0x6 +#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) +/* Privileged Read Only, Unprivileged Read Only */ +#define RO 0x7 +#define RO_Msk ((RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) + +/* Attribute flag for not-allowing execution (eXecute Never) */ +#define NOT_EXEC MPU_RASR_XN_Msk + +/* The following definitions are for internal use in arm_mpu.h. */ +#define STRONGLY_ORDERED_SHAREABLE MPU_RASR_S_Msk +#define DEVICE_SHAREABLE (MPU_RASR_B_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE \ + (MPU_RASR_C_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE MPU_RASR_C_Msk +#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE \ + (MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE \ + (MPU_RASR_C_Msk | MPU_RASR_B_Msk) +#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE \ + ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE \ + (1 << MPU_RASR_TEX_Pos) +#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE \ + ((1 << MPU_RASR_TEX_Pos) |\ + MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk) +#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE \ + ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk) +#define DEVICE_NON_SHAREABLE (2 << MPU_RASR_TEX_Pos) + +/* Bit-masks to disable sub-regions. */ +#define SUB_REGION_0_DISABLED ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_1_DISABLED ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_2_DISABLED ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_3_DISABLED ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_4_DISABLED ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_5_DISABLED ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_6_DISABLED ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) +#define SUB_REGION_7_DISABLED ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) + + +#define REGION_SIZE(size) ((ARM_MPU_REGION_SIZE_ ## size \ + << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + +#define REGION_32B REGION_SIZE(32B) +#define REGION_64B REGION_SIZE(64B) +#define REGION_128B REGION_SIZE(128B) +#define REGION_256B REGION_SIZE(256B) +#define REGION_512B REGION_SIZE(512B) +#define REGION_1K REGION_SIZE(1KB) +#define REGION_2K REGION_SIZE(2KB) +#define REGION_4K REGION_SIZE(4KB) +#define REGION_8K REGION_SIZE(8KB) +#define REGION_16K REGION_SIZE(16KB) +#define REGION_32K REGION_SIZE(32KB) +#define REGION_64K REGION_SIZE(64KB) +#define REGION_128K REGION_SIZE(128KB) +#define REGION_256K REGION_SIZE(256KB) +#define REGION_512K REGION_SIZE(512KB) +#define REGION_1M REGION_SIZE(1MB) +#define REGION_2M REGION_SIZE(2MB) +#define REGION_4M REGION_SIZE(4MB) +#define REGION_8M REGION_SIZE(8MB) +#define REGION_16M REGION_SIZE(16MB) +#define REGION_32M REGION_SIZE(32MB) +#define REGION_64M REGION_SIZE(64MB) +#define REGION_128M REGION_SIZE(128MB) +#define REGION_256M REGION_SIZE(256MB) +#define REGION_512M REGION_SIZE(512MB) +#define REGION_1G REGION_SIZE(1GB) +#define REGION_2G REGION_SIZE(2GB) +#define REGION_4G REGION_SIZE(4GB) + +/* Some helper defines for common regions */ +#define REGION_RAM_ATTR(size) \ +{ \ + (NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \ + MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ +} +#define REGION_RAM_NOCACHE_ATTR(size) \ +{ \ + (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ + MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ +} +#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) +#define REGION_FLASH_ATTR(size) \ +{ \ + (NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | \ + P_RW_U_RO_Msk) \ +} +#else +#define REGION_FLASH_ATTR(size) \ +{ \ + (NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | RO_Msk) \ +} +#endif +#define REGION_PPB_ATTR(size) { (STRONGLY_ORDERED_SHAREABLE | size | \ + P_RW_U_NA_Msk) } +#define REGION_IO_ATTR(size) { (DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk) } + +struct arm_mpu_region_attr { + /* Attributes belonging to RASR (including the encoded region size) */ + uint32_t rasr; +}; + +typedef struct arm_mpu_region_attr arm_mpu_region_attr_t; + +/* Typedef for the k_mem_partition attribute */ +typedef struct { + uint32_t rasr_attr; +} k_mem_partition_attr_t; + +/* Read-Write access permission attributes */ +#define _K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS_Msk | NOT_EXEC) +#define _K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW_Msk | NOT_EXEC) +#define _K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO_Msk | NOT_EXEC) +#define _K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA_Msk | NOT_EXEC) +#define _K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO_Msk | NOT_EXEC) +#define _K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA_Msk | NOT_EXEC) + +/* Execution-allowed attributes */ +#define _K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW_Msk) +#define _K_MEM_PARTITION_P_RWX_U_RX (P_RW_U_RO_Msk) +#define _K_MEM_PARTITION_P_RX_U_RX (P_RO_U_RO_Msk) + +/* Kernel macros for memory attribution + * (access permissions and cache-ability). + * + * The macros are to be stored in k_mem_partition_attr_t + * objects. The format of k_mem_partition_attr_t is an + * "1-1" mapping of the ARMv7-M MPU RASR attribute register + * fields (excluding the and bit-fields). + */ + +/* Read-Write access permission attributes (default cache-ability) */ +#define K_MEM_PARTITION_P_NA_U_NA ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_NA_U_NA | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RW_U_RW | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RW_U_RO ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RW_U_RO | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RW_U_NA | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RO_U_RO | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RO_U_NA | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) + +/* Execution-allowed attributes (default-cacheability) */ +#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RWX_U_RWX | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RWX_U_RX ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RWX_U_RX | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) +#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \ + { _K_MEM_PARTITION_P_RX_U_RX | \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}) + +/* + * @brief Evaluate Write-ability + * + * Evaluate whether the access permissions include write-ability. + * + * @param attr The k_mem_partition_attr_t object holding the + * MPU attributes to be checked against write-ability. + */ +#define K_MEM_PARTITION_IS_WRITABLE(attr) \ + ({ \ + int __is_writable__; \ + switch (attr.rasr_attr & MPU_RASR_AP_Msk) { \ + case P_RW_U_RW_Msk: \ + case P_RW_U_RO_Msk: \ + case P_RW_U_NA_Msk: \ + __is_writable__ = 1; \ + break; \ + default: \ + __is_writable__ = 0; \ + } \ + __is_writable__; \ + }) + +/* + * @brief Evaluate Execution allowance + * + * Evaluate whether the access permissions include execution. + * + * @param attr The k_mem_partition_attr_t object holding the + * MPU attributes to be checked against execution + * allowance. + */ +#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ + (!((attr.rasr_attr) & (NOT_EXEC))) + +/* Attributes for no-cache enabling (share-ability is selected by default) */ + +#define K_MEM_PARTITION_P_NA_U_NA_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_NA_U_NA \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RW_U_RW \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RW_U_RO_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RW_U_RO \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RW_U_NA \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RO_U_RO \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RO_U_NA \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) + +#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RWX_U_RWX \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RWX_U_RX_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RWX_U_RX \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) +#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE ((k_mem_partition_attr_t) \ + {(_K_MEM_PARTITION_P_RX_U_RX \ + | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)}) + +#endif /* _ASMLANGUAGE */ + +#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ + BUILD_ASSERT(!(((size) & ((size) - 1))) && \ + (size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \ + !((uint32_t)(start) & ((size) - 1)), \ + "the size of the partition must be power of 2" \ + " and greater than or equal to the minimum MPU region size." \ + "start address of the partition must align with size.") diff --git a/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h b/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h new file mode 100644 index 00000000000..c4535699f0f --- /dev/null +++ b/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2018 Linaro Limited. + * Copyright (c) 2018 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ASMLANGUAGE + +#include + +/* Convenience macros to represent the ARMv8-M-specific + * configuration for memory access permission and + * cache-ability attribution. + */ + +/* Privileged No Access, Unprivileged No Access */ +/*#define NO_ACCESS 0x0 */ +/*#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */ +/* Privileged No Access, Unprivileged No Access */ +/*#define P_NA_U_NA 0x0 */ +/*#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */ +/* Privileged Read Write, Unprivileged No Access */ +#define P_RW_U_NA 0x0 +#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Only */ +/*#define P_RW_U_RO 0x2 */ +/*#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)*/ +/* Privileged Read Write, Unprivileged Read Write */ +#define P_RW_U_RW 0x1 +#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) +/* Privileged Read Write, Unprivileged Read Write */ +#define FULL_ACCESS 0x1 +#define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) +/* Privileged Read Only, Unprivileged No Access */ +#define P_RO_U_NA 0x2 +#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) +/* Privileged Read Only, Unprivileged Read Only */ +#define P_RO_U_RO 0x3 +#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) +/* Privileged Read Only, Unprivileged Read Only */ +#define RO 0x3 +#define RO_Msk ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) + +/* Attribute flag for not-allowing execution (eXecute Never) */ +#define NOT_EXEC MPU_RBAR_XN_Msk + +/* Attribute flags for share-ability */ +#define NON_SHAREABLE 0x0 +#define NON_SHAREABLE_Msk \ + ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) +#define OUTER_SHAREABLE 0x2 +#define OUTER_SHAREABLE_Msk \ + ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) +#define INNER_SHAREABLE 0x3 +#define INNER_SHAREABLE_Msk \ + ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) + +/* Helper define to calculate the region limit address. */ +#define REGION_LIMIT_ADDR(base, size) \ + (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk) + + +/* Attribute flags for cache-ability */ + +/* Read/Write Allocation Configurations for Cacheable Memory */ +#define R_NON_W_NON 0x0 /* Do not allocate Read/Write */ +#define R_NON_W_ALLOC 0x1 /* Do not allocate Read, Allocate Write */ +#define R_ALLOC_W_NON 0x2 /* Allocate Read, Do not allocate Write */ +#define R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */ + +/* Memory Attributes for Normal Memory */ +#define NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */ +#define NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */ +#define NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable */ + +#define NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */ +#define NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */ +#define NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable */ + +#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS \ + ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) \ + | \ + (NORMAL_I_WT_NT | R_ALLOC_W_NON)) \ + +#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS \ + ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) \ + | \ + (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC)) + +#define NORMAL_OUTER_INNER_NON_CACHEABLE \ + ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) \ + | \ + (NORMAL_I_NON_C | R_NON_W_NON)) + +/* Common cache-ability configuration for Flash, SRAM regions */ +#define MPU_CACHE_ATTRIBUTES_FLASH \ + NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS +#define MPU_CACHE_ATTRIBUTES_SRAM \ + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS +#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE \ + NORMAL_OUTER_INNER_NON_CACHEABLE + +/* Global MAIR configurations */ +#define MPU_MAIR_ATTR_FLASH MPU_CACHE_ATTRIBUTES_FLASH +#define MPU_MAIR_INDEX_FLASH 0 +#define MPU_MAIR_ATTR_SRAM MPU_CACHE_ATTRIBUTES_SRAM +#define MPU_MAIR_INDEX_SRAM 1 +#define MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE +#define MPU_MAIR_INDEX_SRAM_NOCACHE 2 + +/* Some helper defines for common regions. + * + * Note that the ARMv8-M MPU architecture requires that the + * enabled MPU regions are non-overlapping. Therefore, it is + * recommended to use these helper defines only for configuring + * fixed MPU regions at build-time (i.e. regions that are not + * expected to be re-programmed or re-adjusted at run-time so + * that they do not overlap with other MPU regions). + */ +#define REGION_RAM_ATTR(base, size) \ + {\ + .rbar = NOT_EXEC | \ + P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ + } + +#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) +/* Note that the access permissions allow for un-privileged writes, contrary + * to ARMv7-M where un-privileged code has Read-Only permissions. + */ +#define REGION_FLASH_ATTR(base, size) \ + {\ + .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_FLASH, \ + .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ + } +#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */ +#define REGION_FLASH_ATTR(base, size) \ + {\ + .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_FLASH, \ + .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ + } +#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */ + + +struct arm_mpu_region_attr { + /* Attributes belonging to RBAR */ + uint8_t rbar: 5; + /* MAIR index for attribute indirection */ + uint8_t mair_idx: 3; + /* Region Limit Address value to be written to the RLAR register. */ + uint32_t r_limit; +}; + +typedef struct arm_mpu_region_attr arm_mpu_region_attr_t; + +/* Typedef for the k_mem_partition attribute */ +typedef struct { + uint16_t rbar; + uint16_t mair_idx; +} k_mem_partition_attr_t; + +/* Kernel macros for memory attribution + * (access permissions and cache-ability). + * + * The macros are to be stored in k_mem_partition_attr_t + * objects. The format of a k_mem_partition_attr_t object + * is as follows: field contains a direct mapping + * of the and bit-fields of the RBAR register; + * field contains a direct mapping of AttrIdx + * bit-field, stored in RLAR register. + */ + +/* Read-Write access permission attributes */ +#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \ + {(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) +#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \ + {(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) +#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \ + {(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) +#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \ + {(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM}) + +/* Execution-allowed attributes */ +#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \ + {(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM}) +#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \ + {(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM}) + +/* + * @brief Evaluate Write-ability + * + * Evaluate whether the access permissions include write-ability. + * + * @param attr The k_mem_partition_attr_t object holding the + * MPU attributes to be checked against write-ability. + */ +#define K_MEM_PARTITION_IS_WRITABLE(attr) \ + ({ \ + int __is_writable__; \ + switch (attr.rbar & MPU_RBAR_AP_Msk) { \ + case P_RW_U_RW_Msk: \ + case P_RW_U_NA_Msk: \ + __is_writable__ = 1; \ + break; \ + default: \ + __is_writable__ = 0; \ + } \ + __is_writable__; \ + }) + +/* + * @brief Evaluate Execution allowance + * + * Evaluate whether the access permissions include execution. + * + * @param attr The k_mem_partition_attr_t object holding the + * MPU attributes to be checked against execution + * allowance. + */ +#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ + (!((attr.rbar) & (NOT_EXEC))) + +/* Attributes for no-cache enabling (share-ability is selected by default) */ + +/* Read-Write access permission attributes */ +#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE ((k_mem_partition_attr_t) \ + {(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ + MPU_MAIR_INDEX_SRAM_NOCACHE}) +#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE ((k_mem_partition_attr_t) \ + {(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ + MPU_MAIR_INDEX_SRAM_NOCACHE}) +#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE ((k_mem_partition_attr_t) \ + {(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ + MPU_MAIR_INDEX_SRAM_NOCACHE}) +#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE ((k_mem_partition_attr_t) \ + {(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \ + MPU_MAIR_INDEX_SRAM_NOCACHE}) + +/* Execution-allowed attributes */ +#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE ((k_mem_partition_attr_t) \ + {(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk), MPU_MAIR_INDEX_SRAM_NOCACHE}) +#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE ((k_mem_partition_attr_t) \ + {(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk), MPU_MAIR_INDEX_SRAM_NOCACHE}) + +#endif /* _ASMLANGUAGE */ + +#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ + BUILD_ASSERT((size > 0) && ((uint32_t)start % \ + CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \ + ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \ + " the start and size of the partition must align " \ + "with the minimum MPU region size.") diff --git a/include/arch/arm/aarch32/mpu/nxp_mpu.h b/include/arch/arm/aarch32/mpu/nxp_mpu.h new file mode 100644 index 00000000000..b1f5de23514 --- /dev/null +++ b/include/arch/arm/aarch32/mpu/nxp_mpu.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_MPU_NXP_MPU_H_ +#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_MPU_NXP_MPU_H_ + +#ifndef _ASMLANGUAGE + +#include + +#define NXP_MPU_BASE SYSMPU_BASE + +#define NXP_MPU_REGION_NUMBER 12 + +/* Bus Master User Mode Access */ +#define UM_READ 4 +#define UM_WRITE 2 +#define UM_EXEC 1 + +#define BM0_UM_SHIFT 0 +#define BM1_UM_SHIFT 6 +#define BM2_UM_SHIFT 12 +#define BM3_UM_SHIFT 18 + +/* Bus Master Supervisor Mode Access */ +#define SM_RWX_ALLOW 0 +#define SM_RX_ALLOW 1 +#define SM_RW_ALLOW 2 +#define SM_SAME_AS_UM 3 + +#define BM0_SM_SHIFT 3 +#define BM1_SM_SHIFT 9 +#define BM2_SM_SHIFT 15 +#define BM3_SM_SHIFT 21 + +#define BM4_WE_SHIFT 24 +#define BM4_RE_SHIFT 25 + +#ifdef CONFIG_USB_KINETIS +#define BM4_PERMISSIONS ((1 << BM4_RE_SHIFT) | (1 << BM4_WE_SHIFT)) +#else +#define BM4_PERMISSIONS 0 +#endif + +/* Read Attribute */ +#define MPU_REGION_READ ((UM_READ << BM0_UM_SHIFT) | \ + (UM_READ << BM1_UM_SHIFT) | \ + (UM_READ << BM2_UM_SHIFT) | \ + (UM_READ << BM3_UM_SHIFT)) + +/* Write Attribute */ +#define MPU_REGION_WRITE ((UM_WRITE << BM0_UM_SHIFT) | \ + (UM_WRITE << BM1_UM_SHIFT) | \ + (UM_WRITE << BM2_UM_SHIFT) | \ + (UM_WRITE << BM3_UM_SHIFT)) + +/* Execute Attribute */ +#define MPU_REGION_EXEC ((UM_EXEC << BM0_UM_SHIFT) | \ + (UM_EXEC << BM1_UM_SHIFT) | \ + (UM_EXEC << BM2_UM_SHIFT) | \ + (UM_EXEC << BM3_UM_SHIFT)) + +/* Super User Attributes */ +#define MPU_REGION_SU ((SM_SAME_AS_UM << BM0_SM_SHIFT) | \ + (SM_SAME_AS_UM << BM1_SM_SHIFT) | \ + (SM_SAME_AS_UM << BM2_SM_SHIFT) | \ + (SM_SAME_AS_UM << BM3_SM_SHIFT)) + +#define MPU_REGION_SU_RX ((SM_RX_ALLOW << BM0_SM_SHIFT) | \ + (SM_RX_ALLOW << BM1_SM_SHIFT) | \ + (SM_RX_ALLOW << BM2_SM_SHIFT) | \ + (SM_RX_ALLOW << BM3_SM_SHIFT)) + +#define MPU_REGION_SU_RW ((SM_RW_ALLOW << BM0_SM_SHIFT) | \ + (SM_RW_ALLOW << BM1_SM_SHIFT) | \ + (SM_RW_ALLOW << BM2_SM_SHIFT) | \ + (SM_RW_ALLOW << BM3_SM_SHIFT)) + +#define MPU_REGION_SU_RWX ((SM_RWX_ALLOW << BM0_SM_SHIFT) | \ + (SM_RWX_ALLOW << BM1_SM_SHIFT) | \ + (SM_RWX_ALLOW << BM2_SM_SHIFT) | \ + (SM_RWX_ALLOW << BM3_SM_SHIFT)) + +/* The ENDADDR field has the last 5 bit reserved and set to 1 */ +#define ENDADDR_ROUND(x) (x - 0x1F) + +#define REGION_USER_MODE_ATTR {(MPU_REGION_READ | \ + MPU_REGION_WRITE | \ + MPU_REGION_SU)} + +/* Some helper defines for common regions */ +#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) +#define REGION_RAM_ATTR {((MPU_REGION_SU_RWX) | \ + ((UM_READ | UM_WRITE | UM_EXEC) << BM3_UM_SHIFT) | \ + (BM4_PERMISSIONS))} + +#define REGION_FLASH_ATTR {(MPU_REGION_SU_RWX)} + +#else +#define REGION_RAM_ATTR {((MPU_REGION_SU_RW) | \ + ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | \ + (BM4_PERMISSIONS))} + +#define REGION_FLASH_ATTR {(MPU_REGION_READ | \ + MPU_REGION_EXEC | \ + MPU_REGION_SU)} +#endif + +#define REGION_IO_ATTR {(MPU_REGION_READ | \ + MPU_REGION_WRITE | \ + MPU_REGION_EXEC | \ + MPU_REGION_SU)} + +#define REGION_RO_ATTR {(MPU_REGION_READ | MPU_REGION_SU)} + +#define REGION_USER_RO_ATTR {(MPU_REGION_READ | \ + MPU_REGION_SU)} + +/* ENET (Master 3) and USB (Master 4) devices will not be able +to access RAM when the region is dynamically disabled in NXP MPU. +DEBUGGER (Master 1) can't be disabled in Region 0. */ +#define REGION_DEBUGGER_AND_DEVICE_ATTR {((MPU_REGION_SU) | \ + ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | \ + (BM4_PERMISSIONS))} + +#define REGION_DEBUG_ATTR {MPU_REGION_SU} + +#define REGION_BACKGROUND_ATTR {MPU_REGION_SU_RW} + +struct nxp_mpu_region_attr { + /* NXP MPU region access permission attributes */ + uint32_t attr; +}; + +typedef struct nxp_mpu_region_attr nxp_mpu_region_attr_t; + +/* Typedef for the k_mem_partition attribute*/ +typedef struct { + uint32_t ap_attr; +} k_mem_partition_attr_t; + +/* Kernel macros for memory attribution + * (access permissions and cache-ability). + * + * The macros are to be stored in k_mem_partition_attr_t + * objects. + */ + +/* Read-Write access permission attributes */ +#define K_MEM_PARTITION_P_NA_U_NA ((k_mem_partition_attr_t) \ + {(MPU_REGION_SU)}) +#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \ + {(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)}) +#define K_MEM_PARTITION_P_RW_U_RO ((k_mem_partition_attr_t) \ + {(MPU_REGION_READ | MPU_REGION_SU_RW)}) +#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \ + {(MPU_REGION_SU_RW)}) +#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \ + {(MPU_REGION_READ | MPU_REGION_SU)}) +#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \ + {(MPU_REGION_SU_RX)}) + +/* Execution-allowed attributes */ +#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \ + {(MPU_REGION_READ | MPU_REGION_WRITE | \ + MPU_REGION_EXEC | MPU_REGION_SU)}) +#define K_MEM_PARTITION_P_RWX_U_RX ((k_mem_partition_attr_t) \ + {(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU_RWX)}) +#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \ + {(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)}) + +/* + * @brief Evaluate Write-ability + * + * Evaluate whether the access permissions include write-ability. + * + * @param attr The k_mem_partition_attr_t object holding the + * MPU attributes to be checked against write-ability. + */ +#define K_MEM_PARTITION_IS_WRITABLE(attr) \ + ({ \ + int __is_writable__; \ + switch (attr.ap_attr) { \ + case MPU_REGION_WRITE: \ + case MPU_REGION_SU_RW: \ + __is_writable__ = 1; \ + break; \ + default: \ + __is_writable__ = 0; \ + } \ + __is_writable__; \ + }) + +/* + * @brief Evaluate Execution allowance + * + * Evaluate whether the access permissions include execution. + * + * @param attr The k_mem_partition_attr_t object holding the + * MPU attributes to be checked against execution + * allowance. + */ +#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \ + ({ \ + int __is_executable__; \ + switch (attr.ap_attr) { \ + case MPU_REGION_SU_RX: \ + case MPU_REGION_EXEC: \ + __is_executable__ = 1; \ + break; \ + default: \ + __is_executable__ = 0; \ + } \ + __is_executable__; \ + }) + + +/* Region definition data structure */ +struct nxp_mpu_region { + /* Region Base Address */ + uint32_t base; + /* Region End Address */ + uint32_t end; + /* Region Name */ + const char *name; + /* Region Attributes */ + nxp_mpu_region_attr_t attr; +}; + +#define MPU_REGION_ENTRY(_name, _base, _end, _attr) \ + {\ + .name = _name, \ + .base = _base, \ + .end = _end, \ + .attr = _attr, \ + } + +/* MPU configuration data structure */ +struct nxp_mpu_config { + /* Number of regions */ + uint32_t num_regions; + /* Regions */ + const struct nxp_mpu_region *mpu_regions; + /* SRAM Region */ + uint32_t sram_region; +}; + +/* Reference to the MPU configuration. + * + * This struct is defined and populated for each SoC (in the SoC definition), + * and holds the build-time configuration information for the fixed MPU + * regions enabled during kernel initialization. Dynamic MPU regions (e.g. + * for Thread Stack, Stack Guards, etc.) are programmed during runtime, thus, + * not kept here. + */ +extern const struct nxp_mpu_config mpu_config; + +#endif /* _ASMLANGUAGE */ + +#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \ + BUILD_ASSERT((size) % \ + CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0 && \ + (size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \ + (uint32_t)(start) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0, \ + "the size of the partition must align with minimum MPU \ + region size" \ + " and greater than or equal to minimum MPU region size." \ + "start address of the partition must align with minimum MPU \ + region size.") + +#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_MPU_NXP_MPU_H_ */