diff --git a/dts/bindings/cpu/wch,qingke-v4b.yml b/dts/bindings/cpu/wch,qingke-v4b.yml new file mode 100644 index 00000000000..47844a0b1ac --- /dev/null +++ b/dts/bindings/cpu/wch,qingke-v4b.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +description: WCH QingKe V4B RISC-V MCU + +compatible: "wch,qingke-v4b" + +include: riscv,cpus.yaml diff --git a/dts/riscv/wch/ch32v203/ch32v203.dtsi b/dts/riscv/wch/ch32v203/ch32v203.dtsi new file mode 100644 index 00000000000..d883895ed44 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203.dtsi @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hse-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hsi-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + + pll: pll { + #clock-cells = <0>; + compatible = "wch,ch32v20x_30x-pll-clock"; + mul = <15>; + status = "disabled"; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + flash: flash-controller@40022000 { + compatible = "wch,ch32v20x_30x-flash-controller"; + reg = <0x40022000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_K(224)>; + }; + }; + + pwr: pwr@40007000 { + compatible = "wch,pwr"; + reg = <0x40007000 16>; + }; + + pinctrl: pin-controller@40010000 { + compatible = "wch,20x_30x-afio"; + reg = <0x40010000 16>; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@40010800 { + compatible = "wch,gpio"; + reg = <0x40010800 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>; + }; + + gpiob: gpio@40010C00 { + compatible = "wch,gpio"; + reg = <0x40010C00 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>; + }; + + gpioc: gpio@40011000 { + compatible = "wch,gpio"; + reg = <0x40011000 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>; + }; + + gpiod: gpio@40011400 { + compatible = "wch,gpio"; + reg = <0x40011400 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>; + }; + }; + + usart1: uart@40013800 { + compatible = "wch,usart"; + reg = <0x40013800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>; + interrupt-parent = <&pfic>; + interrupts = <53>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "wch,usart"; + reg = <0x40004400 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>; + interrupt-parent = <&pfic>; + interrupts = <54>; + status = "disabled"; + }; + + rcc: rcc@40021000 { + compatible = "wch,rcc"; + reg = <0x40021000 16>; + #clock-cells = <1>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203c6t.dtsi b/dts/riscv/wch/ch32v203/ch32v203c6t.dtsi new file mode 100644 index 00000000000..a29044c64d8 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c6t.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioc { + gpio-reserved-ranges = <0 13>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203c6u.dtsi b/dts/riscv/wch/ch32v203/ch32v203c6u.dtsi new file mode 100644 index 00000000000..894e0dcc662 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c6u.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/riscv/wch/ch32v203/ch32v203c8t.dtsi b/dts/riscv/wch/ch32v203/ch32v203c8t.dtsi new file mode 100644 index 00000000000..b0e3e57c572 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c8t.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioc { + gpio-reserved-ranges = <0 13>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; + +/ { + soc { + usart3: uart@40004800 { + compatible = "wch,usart"; + reg = <0x40004800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>; + interrupt-parent = <&pfic>; + interrupts = <55>; + status = "disabled"; + }; + + usart4: uart@40004c00 { + compatible = "wch,usart"; + reg = <0x40004C00 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>; + interrupt-parent = <&pfic>; + interrupts = <68>; + status = "disabled"; + }; + }; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203c8u.dtsi b/dts/riscv/wch/ch32v203/ch32v203c8u.dtsi new file mode 100644 index 00000000000..5ba2af0914a --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203c8u.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/riscv/wch/ch32v203/ch32v203f6p.dtsi b/dts/riscv/wch/ch32v203/ch32v203f6p.dtsi new file mode 100644 index 00000000000..a3f58281451 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203f6p.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <8 11>, <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <0 1>, <2 8>, <9 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203f8p.dtsi b/dts/riscv/wch/ch32v203/ch32v203f8p.dtsi new file mode 100644 index 00000000000..cbb1ea6d71e --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203f8p.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <11 13>, <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <1 6>, <8 13>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <0 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203f8u.dtsi b/dts/riscv/wch/ch32v203/ch32v203f8u.dtsi new file mode 100644 index 00000000000..ae506ab14ce --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203f8u.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <11 13>, <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <2 10>, <12 14>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <0 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203g6u.dtsi b/dts/riscv/wch/ch32v203/ch32v203g6u.dtsi new file mode 100644 index 00000000000..82aa5f50b6a --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203g6u.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <8 9>; +}; + +&gpiob { + gpio-reserved-ranges = <2 3>, <10 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203g8r.dtsi b/dts/riscv/wch/ch32v203/ch32v203g8r.dtsi new file mode 100644 index 00000000000..750a2a50da4 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203g8r.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <15 16>; +}; + +&gpiob { + gpio-reserved-ranges = <2 6>, <9 10>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <0 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203k6t.dtsi b/dts/riscv/wch/ch32v203/ch32v203k6t.dtsi new file mode 100644 index 00000000000..9dc0653c508 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203k6t.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiob { + gpio-reserved-ranges = <9 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(10)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203k8t.dtsi b/dts/riscv/wch/ch32v203/ch32v203k8t.dtsi new file mode 100644 index 00000000000..f4d5780f647 --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203k8t.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiob { + gpio-reserved-ranges = <9 16>; +}; + +&gpioc { + gpio-reserved-ranges = <0 16>; +}; + +&gpiod { + gpio-reserved-ranges = <2 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(20)>; +}; diff --git a/dts/riscv/wch/ch32v203/ch32v203rbt.dtsi b/dts/riscv/wch/ch32v203/ch32v203rbt.dtsi new file mode 100644 index 00000000000..465c5b1b88a --- /dev/null +++ b/dts/riscv/wch/ch32v203/ch32v203rbt.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiod { + gpio-reserved-ranges = <3 16>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(64)>; +}; + +soc { + usart3: uart@40004800 { + compatible = "wch,usart"; + reg = <0x40004800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>; + interrupt-parent = <&pfic>; + interrupts = <55>; + status = "disabled"; + }; + + usart4: uart@40004c00 { + compatible = "wch,usart"; + reg = <0x40004C00 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>; + interrupt-parent = <&pfic>; + interrupts = <68>; + status = "disabled"; + }; +}; diff --git a/dts/riscv/wch/qingke-v4b.dtsi b/dts/riscv/wch/qingke-v4b.dtsi new file mode 100644 index 00000000000..0fb20ef7e25 --- /dev/null +++ b/dts/riscv/wch/qingke-v4b.dtsi @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "wch,qingke-v4b"; + reg = <0>; + riscv,isa = "rv32imac_zicsr_zifencei"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + pfic: interrupt-controller@e000e000 { + compatible = "wch,pfic"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe000e000 0x10>; + status = "okay"; + }; + + systick: systimer@e000f000 { + compatible = "wch,systick"; + reg = <0xe000f000 0x10>; + status = "okay"; + interrupt-parent = <&pfic>; + interrupts = <12>; + }; + }; +};