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boards: opta: ADC support

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A valid device tree configuration is provided for the ADCs of the 8 input
channels and the sample adc_dt works out of the box. Obviously this is
not the only possible configuration but it provides a good template for
further customization without the need to lookup the ADC GPIOs and
connections in the schematics.

Signed-off-by: Federico Di Gregorio <fog@dndg.it>
This commit is contained in:
Federico Di Gregorio 2024-10-17 15:29:12 +02:00 • committed by Anas Nashif
commit 1f5a1b50fa
2 changed files with 130 additions and 0 deletions
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98
boards/arduino/opta/arduino_opta-common.dtsi
View file

@ -103,3 +103,101 @@
re-gpios = <&gpiob 13 GPIO_ACTIVE_LOW>;
};
};
&adc1 {
pinctrl-0 = <&adc1_inp0_pa0_c &adc1_inp6_pf12>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
vref-mv = <10000>;
#address-cells = <1>;
#size-cells = <0>;
a0: channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
a2: channel@6 {
reg = <6>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
};
&adc2 {
pinctrl-0 = <&adc2_inp9_pb0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
vref-mv = <10000>;
#address-cells = <1>;
#size-cells = <0>;
a3: channel@9 {
reg = <9>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
};
&adc3 {
pinctrl-0 = <&adc3_inp6_pf10 &adc3_inp7_pf8 &adc3_inp8_pf6 &adc3_inp9_pf4 &adc3_inp0_pc2_c>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
vref-mv = <10000>;
#address-cells = <1>;
#size-cells = <0>;
a1: channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
a4: channel@6 {
reg = <6>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
a5: channel@7 {
reg = <7>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
a6: channel@8 {
reg = <8>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
a7: channel@9 {
reg = <9>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <16>;
};
};

32
samples/drivers/adc/adc_dt/boards/arduino_opta_stm32h747xx_m7.overlay Normal file
View file

@ -0,0 +1,32 @@
/*
* Copyright (c) 2021 STMicroelectronics
* Copyright (c) 2024 DNDG srl
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
zephyr,user {
io-channels =
<&adc1 0>, /* I1 */
<&adc3 0>, /* I2 */
<&adc1 6>, /* I3 */
<&adc2 9>, /* I4 */
<&adc3 6>, /* I5 */
<&adc3 7>, /* I6 */
<&adc3 8>, /* I7 */
<&adc3 9>; /* I8 */
};
};
&adc1 {
status ="okay";
};
&adc2 {
status ="okay";
};
&adc3 {
status = "okay";
};