From 1ed5ba7720b89ef553204796b088efa5a79fa593 Mon Sep 17 00:00:00 2001 From: Piotr Mienkowski Date: Wed, 26 Jan 2022 23:24:40 +0100 Subject: [PATCH] drivers: i2s_sam_ssc: fix cache coherency in dma_rx_callback Invalidate the cache before the RX data block is passed to the DMA engine and not after it is received. If the RX data block contains dirty cache lines they can be flushed anytime, overwriting legitimate data that have been prefilled by the DMA module. Signed-off-by: Piotr Mienkowski --- drivers/i2s/i2s_sam_ssc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/i2s/i2s_sam_ssc.c b/drivers/i2s/i2s_sam_ssc.c index 8a3ffbd982c..db7a6275d01 100644 --- a/drivers/i2s/i2s_sam_ssc.c +++ b/drivers/i2s/i2s_sam_ssc.c @@ -220,9 +220,6 @@ static void dma_rx_callback(const struct device *dma_dev, void *user_data, goto rx_disable; } - /* Assure cache coherency after DMA write operation */ - DCACHE_INVALIDATE(stream->mem_block, stream->cfg.block_size); - /* All block data received */ ret = queue_put(&stream->mem_block_queue, stream->mem_block, stream->cfg.block_size); @@ -247,6 +244,9 @@ static void dma_rx_callback(const struct device *dma_dev, void *user_data, goto rx_disable; } + /* Assure cache coherency before DMA write operation */ + DCACHE_INVALIDATE(stream->mem_block, stream->cfg.block_size); + ret = reload_dma(dev_cfg->dev_dma, stream->dma_channel, (void *)&(ssc->SSC_RHR), stream->mem_block, stream->cfg.block_size);