From 1e9c7a9ad61582e94c0d794c6fb0952901bcbd79 Mon Sep 17 00:00:00 2001 From: Alexander Razinkov Date: Wed, 16 Nov 2022 17:22:01 +0300 Subject: [PATCH] drivers: timer: added MTIMER_DIVIDER register initialization Syntacore RISC-V platforms have dedicated MTIMER_DIVIDER register which should be configured during the Timer initialization. The configuration of dedicated MTIMER_DIVIDER register could now be performed during initialization if its address is provided. Signed-off-by: Alexander Razinkov --- drivers/timer/riscv_machine_timer.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c index 1368b85befa..37f50f27a37 100644 --- a/drivers/timer/riscv_machine_timer.c +++ b/drivers/timer/riscv_machine_timer.c @@ -62,6 +62,15 @@ #define MTIMECMP_REG DT_INST_REG_ADDR(0) #define MTIME_REG (DT_INST_REG_ADDR(0) + 8) #define TIMER_IRQN DT_INST_IRQN(0) +/* scr,machine-timer*/ +#elif DT_HAS_COMPAT_STATUS_OKAY(scr_machine_timer) +#define DT_DRV_COMPAT scr_machine_timer +#define MTIMER_HAS_DIVIDER + +#define MTIMEDIV_REG (DT_INST_REG_ADDR(0) + 4) +#define MTIME_REG (DT_INST_REG_ADDR(0) + 8) +#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 16) +#define TIMER_IRQN DT_INST_IRQN(0) #endif #define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \ @@ -103,6 +112,14 @@ static void set_mtimecmp(uint64_t time) #endif } +static void set_divider(void) +{ +#ifdef MTIMER_HAS_DIVIDER + *(volatile uint32_t *)MTIMEDIV_REG = + CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER; +#endif +} + static uint64_t mtime(void) { #ifdef CONFIG_64BIT @@ -207,6 +224,8 @@ static int sys_clock_driver_init(const struct device *dev) { ARG_UNUSED(dev); + set_divider(); + IRQ_CONNECT(TIMER_IRQN, 0, timer_isr, NULL, 0); last_ticks = mtime() / CYC_PER_TICK; last_count = last_ticks * CYC_PER_TICK;