From 1e8fb26b67ce28ba961b43965cab6fc3eb5d7af1 Mon Sep 17 00:00:00 2001 From: Hao Luo Date: Wed, 12 Feb 2025 11:31:41 +0800 Subject: [PATCH] drivers: serial: pl011: Add support for Ambiq Apollo510 SoC UART Added more clock sources for Apollo510 support Signed-off-by: Hao Luo --- drivers/serial/uart_pl011.c | 2 +- drivers/serial/uart_pl011_ambiq.h | 10 ++++++++++ drivers/serial/uart_pl011_registers.h | 1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 7ee021c0bea..624ae45f5c5 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -38,7 +38,7 @@ #include "uart_pl011_ambiq.h" #endif -#if defined(CONFIG_SOC_SERIES_APOLLO3X) +#if defined(CONFIG_SOC_SERIES_APOLLO3X) || defined(CONFIG_SOC_SERIES_APOLLO5X) #define PM_INST_GET(n) PM_DEVICE_DT_INST_GET(n) #else #define PM_INST_GET(n) NULL diff --git a/drivers/serial/uart_pl011_ambiq.h b/drivers/serial/uart_pl011_ambiq.h index 305fc992e7c..c840731c09d 100644 --- a/drivers/serial/uart_pl011_ambiq.h +++ b/drivers/serial/uart_pl011_ambiq.h @@ -37,6 +37,16 @@ static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk) case 24000000: clksel = PL011_CR_AMBIQ_CLKSEL_24MHZ; break; +#if !defined(CONFIG_SOC_SERIES_APOLLO3X) + case 48000000: + clksel = PL011_CR_AMBIQ_CLKSEL_48MHZ; + break; +#if !defined(CONFIG_SOC_SERIES_APOLLO4X) + case AM_HAL_UART_PLLCLK_FREQ: + clksel = PL011_CR_AMBIQ_CLKSEL_PLL; + break; +#endif +#endif default: return -EINVAL; } diff --git a/drivers/serial/uart_pl011_registers.h b/drivers/serial/uart_pl011_registers.h index 6f559d0041b..a46509e18b6 100644 --- a/drivers/serial/uart_pl011_registers.h +++ b/drivers/serial/uart_pl011_registers.h @@ -114,6 +114,7 @@ volatile struct pl011_regs *get_uart(const struct device *dev) #define PL011_CR_AMBIQ_CLKSEL_6MHZ 3 #define PL011_CR_AMBIQ_CLKSEL_3MHZ 4 #define PL011_CR_AMBIQ_CLKSEL_48MHZ 5 +#define PL011_CR_AMBIQ_CLKSEL_PLL 6 /* PL011 Interrupt Fifo Level Select Register */ #define PL011_IFLS_RXIFLSEL_M GENMASK(5, 3)