diff --git a/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1 b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1
new file mode 100644
index 00000000000..c21e240aeaa
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/Kconfig.ek_ra6m1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA6M1
+	select SOC_R7FA6M1AD3CFP
diff --git a/boards/renesas/ek_ra6m1/board.cmake b/boards/renesas/ek_ra6m1/board.cmake
new file mode 100644
index 00000000000..1a34ff99958
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA6M1AD")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra6m1/board.yml b/boards/renesas/ek_ra6m1/board.yml
new file mode 100644
index 00000000000..db68eb8a068
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/board.yml
@@ -0,0 +1,5 @@
+board:
+  name: ek_ra6m1
+  vendor: renesas
+  socs:
+  - name: r7fa6m1ad3cfp
diff --git a/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp b/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp
new file mode 100644
index 00000000000..438d21dc19b
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diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst
new file mode 100644
index 00000000000..454e77352ac
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/doc/index.rst
@@ -0,0 +1,159 @@
+.. _ek_ra6m1:
+
+RA6M1 Evaluation Kit
+####################
+
+Overview
+********
+
+The Renesas RA6M1 microcontroller is the entry point to the Renesas RA6 product
+series for applications that require a high-performance Arm® Cortex®-M4 core at
+a very attractive price point. The RA6M1 is built on a highly efficient 40nm process
+and is supported by an open and flexible ecosystem concept—the Flexible Software
+Package (FSP), built on FreeRTOS—and is expandable to use other RTOSes and middleware.
+The RA6M1 is suitable for IoT applications requiring security, large embedded RAM and
+low power consumption.
+
+The key features of the EK-RA6M1 board are categorized in three groups as follow:
+
+**MCU Native Pin Access**
+- R7FA6M1AD3CFP
+- 100-pin LQFP package
+- 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
+- 256 KB SRAM
+- 512 KB code flash memory
+- 8 KB data flash memory
+
+**Connectivity**
+- A Device USB connector for the Main MCU
+- S124 MCU-based SEGGER J-Link® On-Board interface for debugging and programming of the
+RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external
+debuggers and programmers.
+- Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for
+rapid prototyping
+- Pin headers for access to power and signals for the Main MCU
+
+**Multiple clock sources**
+- Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference
+clocks
+- Additional low-precision clocks are available internal to the Main MCU
+
+**General purpose I/O ports**
+- One jumper to allow measuring of Main MCU current
+- Copper jumpers on PCB bottom side for configuration and access to selected MCU signals
+**Operating voltage**
+- External 5 V input through the Debug USB connector supplies the on-board power regulator to power
+logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate
+locations on the board.
+- A two-color board status LED indicating availability of regulated power and connection status of the J-Link
+interface.
+- A red User LED, controlled by the Main MCU firmware
+- A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer,
+all of which are controlled by the Main MCU firmware
+- MCU reset push-button switch
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- USB Full Speed Debug and Device (micro-AB connector)
+
+.. figure:: ek-ra6m1-board.webp
+	:align: center
+	:alt: RA6M1 Evaluation Kit
+
+	EK-RA6M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+
+Hardware
+********
+Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_
+
+.. figure:: ra6m1-block-diagram.webp
+	:width: 442px
+	:align: center
+	:alt: RA6M1 MCU group feature
+
+	RA6M1 Block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware feature for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_
+
+Supported Features
+==================
+
+The below features are currently supported on Zephyr OS for EK-RA6M1 board:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| MPU       | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| NVIC      | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| UART      | on-chip    | serial               |
++-----------+------------+----------------------+
+
+Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra6m1`` board target configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA6M1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+  1. Connect to J-Link OB via USB port to host PC
+
+  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_
+
+  3. Execute west command
+
+	.. code-block:: console
+
+		west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA6M1AD
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA6M1 Website`_
+- `RA6M1 MCU group Website`_
+
+.. _EK-RA6M1 Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group
+
+.. _RA6M1 MCU group Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra6m1-32-bit-microcontrollers-120mhz-optimized-entry-point-ra6-series
+
+.. _EK-RA6M1 - User's Manual:
+   https://www.renesas.com/us/en/document/mat/ek-ra6m1-v1-users-manual
+
+.. _RA6M1 Group User's Manual Hardware:
+   https://www.renesas.com/us/en/document/mah/renesas-ra6m1-group-users-manual-hardware?r=1054156
+
+.. _Segger Ozone Download:
+   https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp
new file mode 100644
index 00000000000..2f9511bf9a5
Binary files /dev/null and b/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp differ
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
new file mode 100644
index 00000000000..56fa3e26b6a
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci8_default: sci8_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_8, 1, 5)>,
+			<RA_PSEL(RA_PSEL_SCI_8, 1, 4)>;
+		};
+	};
+};
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
new file mode 100644
index 00000000000..013c7d4fa88
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra6/r7fa6m1ad3cfp.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "ek_ra6m1-pinctrl.dtsi"
+
+/ {
+	model = "Renesas EK-RA6M1";
+	compatible = "renesas,ra6m1", "renesas,ra";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart8;
+		zephyr,shell-uart = &uart8;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led1: led1 {
+			gpios = <&ioport1 12 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+	};
+};
+
+&sci8 {
+	pinctrl-0 = <&sci8_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	uart8: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&xtal {
+	clock-frequency = <DT_FREQ_M(20)>;
+	mosel = <0>;
+	#clock-cells = <0>;
+	status = "okay";
+};
+
+&subclk {
+	status = "okay";
+};
+
+&pll {
+	source = <RA_PLL_SOURCE_MAIN_OSC>;
+	div = <RA_PLL_DIV_1>;
+	mul = <20 0>;
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
new file mode 100644
index 00000000000..92e8d569db2
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
@@ -0,0 +1,12 @@
+identifier: ek_ra6m1
+name: Renesas EK-RA6M1
+type: mcu
+arch: arm
+ram: 256
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
new file mode 100644
index 00000000000..8a9dda7f22e
--- /dev/null
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
@@ -0,0 +1,17 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
+
+# Enable GPIO
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_NO_GAP_FILL=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
new file mode 100644
index 00000000000..dd393243085
--- /dev/null
+++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
+
+/ {
+	soc {
+		sram0: memory@1ffe0000 {
+			compatible = "mmio-sram";
+			reg = <0x1ffe0000 DT_SIZE_K(256)>;
+		};
+
+		flash-controller@407e0000 {
+			reg = <0x407e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+			};
+		};
+	};
+
+	clocks: clocks {
+		xtal: clock-xtal {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(12)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			source = <RA_PLL_SOURCE_MAIN_OSC>;
+			div = <RA_PLL_DIV_1>;
+			mul = <20 0>;
+			freq = <DT_FREQ_M(120)>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock {
+			compatible = "renesas,ra-cgc-pclk-block";
+			#clock-cells = <0>;
+			sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			bclk: bclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				bclkout: bclkout {
+					compatible = "renesas,ra-cgc-busclk";
+					clk_out_div = <2>;
+					sdclk = <0>;
+					#clock-cells = <0>;
+				};
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_USB_CLOCK_DIV_5>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};