diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA new file mode 100644 index 00000000000..f008815cc90 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA @@ -0,0 +1,31 @@ +# Kconfig.defconfig.nrf51822_QFAA - Nordic Semiconductor nRF51822 MCU +# +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2016 Nordic Semiconductor ASA +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +if SOC_NRF51822_QFAA + +config SOC + string + default nRF51822_QFAA + +config SRAM_SIZE + default 16 + +config FLASH_SIZE + default 256 + +endif # SOC_NRF51822_QFAA diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB new file mode 100644 index 00000000000..b23a548b344 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB @@ -0,0 +1,31 @@ +# Kconfig.defconfig.nrf51822_QFAB - Nordic Semiconductor nRF51822 MCU +# +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2016 Nordic Semiconductor ASA +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +if SOC_NRF51822_QFAB + +config SOC + string + default nRF51822_QFAB + +config SRAM_SIZE + default 16 + +config FLASH_SIZE + default 128 + +endif # SOC_NRF51822_QFAB diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC new file mode 100644 index 00000000000..9ac707a8bf5 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC @@ -0,0 +1,31 @@ +# Kconfig.defconfig.nrf51822_QFAC - Nordic Semiconductor nRF51822 MCU +# +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2016 Nordic Semiconductor ASA +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +if SOC_NRF51822_QFAC + +config SOC + string + default nRF51822_QFAC + +config SRAM_SIZE + default 32 + +config FLASH_SIZE + default 256 + +endif # SOC_NRF51822_QFAC diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series new file mode 100644 index 00000000000..ae00b03a66a --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series @@ -0,0 +1,43 @@ +# Kconfig.defconfig.series - Nordic Semiconductor nRF5 MCU line +# +# Copyright (c) 2016 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +if SOC_SERIES_NRF51X + +source "arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51*" + +config SOC_SERIES + default nrf51 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 32768 + +config SRAM_BASE_ADDRESS + default 0x20000000 + +config FLASH_BASE_ADDRESS + default 0x00000000 + +config NUM_IRQS + int + default 26 + +config NUM_IRQ_PRIO_BITS + int + default 2 + +endif # SOC_SERIES_NRF51X diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.series b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.series new file mode 100644 index 00000000000..c601c434ea6 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.series @@ -0,0 +1,28 @@ +# Kconfig.series - Nordic Semiconductor nRF5 MCU line +# +# Copyright (c) 2016 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +config SOC_SERIES_NRF51X + bool "Nordic Semiconductor nRF51 series MCU" + select CPU_CORTEX_M + select CPU_CORTEX_M0 + select SOC_FAMILY_NRF5 + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select XIP + select HAS_CMSIS + select HAS_NORDIC_MDK + help + Enable support for NRF51 MCU series diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.soc b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.soc new file mode 100644 index 00000000000..70d9bf84dac --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.soc @@ -0,0 +1,31 @@ +# Kconfig.soc - Nordic Semiconductor nRF51 MCU line +# +# Copyright (c) 2016 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +choice +prompt "nRF51x MCU Selection" +depends on SOC_SERIES_NRF51X + +config SOC_NRF51822_QFAA + bool "NRF51822_QFAA" + +config SOC_NRF51822_QFAB + bool "NRF51822_QFAB" + +config SOC_NRF51822_QFAC + bool "NRF51822_QFAC" + +endchoice diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Makefile b/arch/arm/soc/nordic_nrf5/nrf51/Makefile new file mode 100644 index 00000000000..4be951dbcf1 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/Makefile @@ -0,0 +1,21 @@ +ZEPHYRINCLUDE += -I$(srctree)/arch/arm/soc/nordic_nrf5/include + +ifdef CONFIG_SOC_SERIES_NRF51X +soc-cflags += -DNRF51 +endif + +obj-y += soc.o + +KERNEL_HEX_NAME = $(KERNEL_NAME).hex + +quiet_cmd_gen_hex = HEX $@ + cmd_gen_hex = \ +( \ + $(OBJCOPY) -S -O ihex -R .note -R .comment -R COMMON -R .eh_frame $< $@; \ +) + +$(KERNEL_HEX_NAME): $(KERNEL_ELF_NAME) + $(call cmd,gen_hex) + +zephyr: $(KERNEL_HEX_NAME) +all: $(KERNEL_HEX_NAME) diff --git a/arch/arm/soc/nordic_nrf5/nrf51/linker.ld b/arch/arm/soc/nordic_nrf5/nrf51/linker.ld new file mode 100644 index 00000000000..cf2cfad5942 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/linker.ld @@ -0,0 +1,19 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include diff --git a/arch/arm/soc/nordic_nrf5/nrf51/soc.c b/arch/arm/soc/nordic_nrf5/nrf51/soc.c new file mode 100644 index 00000000000..6c5c7a557f9 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/soc.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2016 Nordic Semiconductor ASA + * Copyright (c) 2016 Linaro Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file + * @brief System/hardware module for Nordic Semiconductor nRF51 family processor + * + * This module provides routines to initialize and support board-level hardware + * for the Nordic Semiconductor nRF51 family processor. + */ + +#include +#include +#include +#include + +#ifdef CONFIG_RUNTIME_NMI +extern void _NmiInit(void); +#define NMI_INIT() _NmiInit() +#else +#define NMI_INIT() +#endif + +#include "nrf.h" + +#define __SYSTEM_CLOCK (16000000UL) + +static bool ftpan_26(void); +static bool ftpan_59(void); + +uint32_t SystemCoreClock __used = __SYSTEM_CLOCK; + +static int nordicsemi_nrf51_init(struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + /* Note: + * Magic numbers below are obtained by reading the registers + * when the SoC was running the SAM-BA bootloader + * (with reserved bits set to 0). + */ + + key = irq_lock(); + + /* Prepare the peripherals for use as indicated by the PAN 26 "System: + * Manual setup is required to enable the use of peripherals" found at + * Product Anomaly document for your device found at + * https://www.nordicsemi.com/. The side effect of executing these + * instructions in the devices that do not need it is that the new + * peripherals in the second generation devices (LPCOMP for example) + * will not be available. + */ + if (ftpan_26()) { + *(volatile uint32_t *)0x40000504 = 0xC007FFDF; + *(volatile uint32_t *)0x40006C18 = 0x00008000; + } + + /* Disable PROTENSET registers under debug, as indicated by PAN 59 + * "MPU: Reset value of DISABLEINDEBUG register is incorrect" found + * at Product Anomaly document for your device found at + * https://www.nordicsemi.com/. + */ + if (ftpan_59()) { + NRF_MPU->DISABLEINDEBUG = + MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << + MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; + } + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +static bool ftpan_26(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && + (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && + (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && + (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && + (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { + return true; + } + } + + return false; +} + +static bool ftpan_59(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && + (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && + (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { + return true; + } + } + + return false; +} + +SYS_INIT(nordicsemi_nrf51_init, PRIMARY, 0); diff --git a/arch/arm/soc/nordic_nrf5/nrf51/soc.h b/arch/arm/soc/nordic_nrf5/nrf51/soc.h new file mode 100644 index 00000000000..c721c7489a4 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf51/soc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016 Linaro Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SoC configuration macros for the Nordic nRF51 family processors. + */ + +#ifndef _NORDICSEMI_NRF51_SOC_H_ +#define _NORDICSEMI_NRF51_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include +#include +#include +#include +#include + +#endif /* !_ASMLANGUAGE */ + +#define NRF51_POWER_RAMON_ADDRESS 0x40000524 +#define NRF51_POWER_RAMONB_ADDRESS 0x40000554 +#define NRF51_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3 + +#endif /* _NORDICSEMI_NRF51_SOC_H_ */