drivers/pwm: Driver for SiFive PWM peripheral
The PWM driver can only control channels 1-3 of the PWM peripheral, not channel 0. This is an artifact of the peripheral's design. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit is contained in:
Nathaniel Graff
Maureen Helm
parent
a49f9ebb2e
commit
1dc3cc7fc6
5 changed files with 292 additions and 0 deletions
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@ -4,6 +4,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_PCA9685 pwm_pca9685.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_DW pwm_dw.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_QMSI pwm_qmsi.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_STM32 pwm_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SIFIVE pwm_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRF5_SW pwm_nrf5_sw.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRFX pwm_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_FTM pwm_mcux_ftm.c)
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@ -40,6 +40,8 @@ source "drivers/pwm/Kconfig.dw"
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source "drivers/pwm/Kconfig.stm32"
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source "drivers/pwm/Kconfig.sifive"
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source "drivers/pwm/Kconfig.nrf5_sw"
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source "drivers/pwm/Kconfig.nrfx"
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25
drivers/pwm/Kconfig.sifive
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25
drivers/pwm/Kconfig.sifive
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@ -0,0 +1,25 @@
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# Kconfig.sifive - SiFive Freedom PWM configuration options
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#
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#
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# Copyright (c) 2018 SiFive Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig PWM_SIFIVE
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bool "SiFive Freedom PWM driver"
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depends on PWM
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depends on SOC_SERIES_RISCV32_SIFIVE_FREEDOM
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depends on HAS_DTS
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help
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Enable the PWM driver for the SiFive Freedom platform
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if PWM_SIFIVE
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config PWM_SIFIVE_INIT_PRIORITY
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int "Init Priority"
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default KERNEL_INIT_PRIORITY_DEVICE
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help
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SiFive PWM Driver Initialization Priority
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endif # PWM_SIFIVE
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252
drivers/pwm/pwm_sifive.c
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252
drivers/pwm/pwm_sifive.c
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@ -0,0 +1,252 @@
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/*
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* Copyright (c) 2018 SiFive Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_LOG_PWM_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_sifive);
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#include <sys_io.h>
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#include <device.h>
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#include <pwm.h>
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/* Macros */
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#define PWM_REG(_config, _offset) ((mem_addr_t) ((_config)->base + _offset))
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/* Register Offsets */
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#define REG_PWMCFG 0x00
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#define REG_PWMCOUNT 0x08
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#define REG_PWMS 0x10
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#define REG_PWMCMP0 0x20
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#define REG_PWMCMP(_channel) (REG_PWMCMP0 + ((_channel) * 0x4))
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/* Number of PWM Channels */
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#define SF_NUMCHANNELS 4
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/* pwmcfg Bit Offsets */
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#define SF_PWMSTICKY 8
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#define SF_PWMZEROCMP 9
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#define SF_PWMDEGLITCH 10
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#define SF_PWMENALWAYS 12
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#define SF_PWMENONESHOT 13
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#define SF_PWMCMPCENTER(_channel) (16 + (_channel))
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#define SF_PWMCMPGANG(_channel) (24 + (_channel))
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#define SF_PWMCMPIP(_channel) (28 + (_channel))
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/* pwmcount scale factor */
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#define SF_PWMSCALEMASK 0xF
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#define SF_PWMSCALE(_val) (SF_PWMSCALEMASK & (_val))
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#define SF_PWMCOUNT_MIN_WIDTH 15
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/* Structure Declarations */
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struct pwm_sifive_data {};
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struct pwm_sifive_cfg {
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u32_t base;
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u32_t f_sys;
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u32_t cmpwidth;
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};
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/* Helper Functions */
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static inline void sys_set_mask(mem_addr_t addr, u32_t mask, u32_t value)
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{
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u32_t temp = sys_read32(addr);
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temp &= ~(mask);
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temp |= value;
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sys_write32(temp, addr);
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}
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/* API Functions */
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static int pwm_sifive_init(struct device *dev)
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{
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const struct pwm_sifive_cfg *config = dev->config->config_info;
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/* When pwms == pwmcmp0, reset the counter */
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sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMZEROCMP);
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/* Enable continuous operation */
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sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMENALWAYS);
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/* Clear IP config bits */
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMSTICKY);
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMDEGLITCH);
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/* Clear all channels */
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for (int i = 0; i < SF_NUMCHANNELS; i++) {
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/* Clear the channel comparator */
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sys_write32(0, PWM_REG(config, REG_PWMCMP(i)));
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/* Clear the compare center and compare gang bits */
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPCENTER(i));
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPGANG(i));
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}
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return 0;
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}
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static int pwm_sifive_pin_set(struct device *dev,
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u32_t pwm,
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u32_t period_cycles,
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u32_t pulse_cycles)
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{
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const struct pwm_sifive_cfg *config = NULL;
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u32_t count_max = 0;
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u32_t max_cmp_val = 0;
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u32_t pwmscale = 0;
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if (dev == NULL) {
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LOG_ERR("The device instance pointer was NULL\n");
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return -EFAULT;
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}
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if (dev->config == NULL) {
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LOG_ERR("The device config pointer was NULL\n");
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return -EFAULT;
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}
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config = dev->config->config_info;
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if (config == NULL) {
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LOG_ERR("The device configuration is NULL\n");
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return -EFAULT;
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}
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if (pwm >= SF_NUMCHANNELS) {
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LOG_ERR("The requested PWM channel %d is invalid\n", pwm);
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return -EINVAL;
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}
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/* Channel 0 sets the period, we can't output PWM with it */
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if ((pwm == 0)) {
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LOG_ERR("PWM channel 0 cannot be configured\n");
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return -ENOTSUP;
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}
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/* We can't support periods greater than we can store in pwmcount */
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count_max = (1 << (config->cmpwidth + SF_PWMCOUNT_MIN_WIDTH)) - 1;
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if (period_cycles > count_max) {
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LOG_ERR("Requested period is %d but maximum is %d\n",
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period_cycles, count_max);
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return -EIO;
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}
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/* Calculate the maximum value that pwmcmpX can be set to */
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max_cmp_val = ((1 << config->cmpwidth) - 1);
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/*
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* Find the minimum value of pwmscale that will allow us to set the
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* requested period
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*/
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while ((period_cycles >> pwmscale) > max_cmp_val) {
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pwmscale++;
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}
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/* Make sure that we can scale that much */
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if (pwmscale > SF_PWMSCALEMASK) {
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LOG_ERR("Requested period is %d but maximum is %d\n",
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period_cycles, max_cmp_val << pwmscale);
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return -EIO;
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}
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if (pulse_cycles > period_cycles) {
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LOG_ERR("Requested pulse %d is longer than period %d\n",
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pulse_cycles, period_cycles);
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return -EIO;
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}
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/* Set the pwmscale field */
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sys_set_mask(PWM_REG(config, REG_PWMCFG),
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SF_PWMSCALEMASK,
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SF_PWMSCALE(pwmscale));
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/* Set the period by setting pwmcmp0 */
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sys_write32((period_cycles >> pwmscale), PWM_REG(config, REG_PWMCMP0));
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/* Set the duty cycle by setting pwmcmpX */
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sys_write32((pulse_cycles >> pwmscale),
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PWM_REG(config, REG_PWMCMP(pwm)));
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LOG_DBG("channel: %d, pwmscale: %d, pwmcmp0: %d, pwmcmp%d: %d",
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pwm,
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pwmscale,
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(period_cycles >> pwmscale),
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pwm,
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(pulse_cycles >> pwmscale));
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return 0;
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}
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static int pwm_sifive_get_cycles_per_sec(struct device *dev,
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u32_t pwm,
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u64_t *cycles)
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{
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const struct pwm_sifive_cfg *config;
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if (dev == NULL) {
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LOG_ERR("The device instance pointer was NULL\n");
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return -EFAULT;
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}
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if (dev->config == NULL) {
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LOG_ERR("The device config pointer was NULL\n");
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return -EFAULT;
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}
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config = dev->config->config_info;
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if (config == NULL) {
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LOG_ERR("The device configuration is NULL\n");
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return -EFAULT;
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}
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/* Fail if we don't have that channel */
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if (pwm >= SF_NUMCHANNELS) {
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return -EINVAL;
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}
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*cycles = config->f_sys;
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return 0;
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}
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/* Device Instantiation */
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static const struct pwm_driver_api pwm_sifive_api = {
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.pin_set = pwm_sifive_pin_set,
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.get_cycles_per_sec = pwm_sifive_get_cycles_per_sec,
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};
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#define PWM_SIFIVE_INIT(n) \
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static struct pwm_sifive_data pwm_sifive_data_##n; \
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static const struct pwm_sifive_cfg pwm_sifive_cfg_##n = { \
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.base = DT_SIFIVE_PWM0_##n##_BASE_ADDRESS, \
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.f_sys = DT_SIFIVE_PWM0_##n##_CLOCK_FREQUENCY, \
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.cmpwidth = DT_SIFIVE_PWM0_##n##_SIFIVE_COMPARE_WIDTH, \
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}; \
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DEVICE_AND_API_INIT(pwm_##n, \
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DT_SIFIVE_PWM0_##n##_LABEL, \
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pwm_sifive_init, \
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&pwm_sifive_data_##n, \
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&pwm_sifive_cfg_##n, \
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POST_KERNEL, \
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CONFIG_PWM_SIFIVE_INIT_PRIORITY, \
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&pwm_sifive_api)
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#ifdef DT_SIFIVE_PWM0_0_LABEL
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PWM_SIFIVE_INIT(0);
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#endif /* DT_SIFIVE_PWM0_0_LABEL */
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#ifdef DT_SIFIVE_PWM0_1_LABEL
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PWM_SIFIVE_INIT(1);
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#endif /* DT_SIFIVE_PWM0_1_LABEL */
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#ifdef DT_SIFIVE_PWM0_2_LABEL
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PWM_SIFIVE_INIT(2);
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#endif /* DT_SIFIVE_PWM0_2_LABEL */
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@ -21,6 +21,12 @@ properties:
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constraint: "sifive,pwm0"
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generation: define
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clock-frequency:
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type: int
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category: optional
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description: Clock frequency information for PWM operation
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generation: define
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reg:
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type: array
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description: mmio register space
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@ -33,6 +39,12 @@ properties:
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description: required interrupts
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generation: define
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sifive,compare-width:
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type: int
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category: required
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description: Width of the PWM comparator in bits
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generation: define
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"#cells":
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- channel
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# period in terms of nanoseconds
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