drivers: pinctrl: add OpenISA RV32M1 pinctrl driver

Add OpenISA RV32M1 pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>

drivers/pinctrl/CMakeLists.txt

@@ -19,3 +19,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)

drivers/pinctrl/Kconfig

@@ -44,5 +44,6 @@ source "drivers/pinctrl/Kconfig.sifive"
 source "drivers/pinctrl/Kconfig.lpc_iocon"
 source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
 source "drivers/pinctrl/Kconfig.esp32"
+source "drivers/pinctrl/Kconfig.rv32m1"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.rv32m1

@@ -0,0 +1,11 @@
+# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_OPENISA_RV32M1_PINCTRL := openisa,rv32m1-pinctrl
+
+config PINCTRL_RV32M1
+	bool "RV32M1 pin controller driver"
+	depends on SOC_OPENISA_RV32M1_RISCV32
+	default $(dt_compat_enabled,$(DT_COMPAT_OPENISA_RV32M1_PINCTRL))
+	help
+	  Enable the RV32M1 pin controller driver.

drivers/pinctrl/pinctrl_rv32m1.c

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT openisa_rv32m1_pinmux
+
+#include <zephyr/drivers/pinctrl.h>
+#include <fsl_clock.h>
+
+/* Port register addresses. */
+static PORT_Type *ports[] = {
+	(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
+	(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
+	(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
+	(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
+	(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
+};
+
+#define PIN(mux) (((mux) & 0xFC00000) >> 22)
+#define PORT(mux) (((mux) & 0xF0000000) >> 28)
+#define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK)
+
+struct pinctrl_rv32m1_config {
+	clock_ip_name_t clock_ip_name;
+};
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	for (uint8_t i = 0; i < pin_cnt; i++) {
+		PORT_Type *base = ports[PORT(pins[i])];
+		uint8_t pin = PIN(pins[i]);
+		uint16_t mux = PINCFG(pins[i]);
+
+		base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux;
+	}
+	return 0;
+}
+
+/* RV32M1 pinmux driver binds to the same DTS nodes,
+ * and handles clock init. Only bind to these nodes if pinmux driver
+ * is disabled.
+ */
+#ifndef CONFIG_PINMUX
+static int pinctrl_rv32m1_init(const struct device *dev)
+{
+	const struct pinctrl_rv32m1_config *config = dev->config;
+
+	CLOCK_EnableClock(config->clock_ip_name);
+
+	return 0;
+}
+
+#define PINCTRL_RV32M1_INIT(n)						\
+	static const struct pinctrl_rv32m1_config pinctrl_rv32m1_##n##_config = {\
+		.clock_ip_name = INST_DT_CLOCK_IP_NAME(n),		\
+	};								\
+									\
+	DEVICE_DT_INST_DEFINE(n,					\
+			    &pinctrl_rv32m1_init,			\
+			    NULL,					\
+			    NULL, &pinctrl_rv32m1_##n##_config,		\
+			    PRE_KERNEL_1,				\
+			    1,						\
+			    NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(PINCTRL_RV32M1_INIT)
+#endif

include/zephyr/dt-bindings/pinctrl/rv32m1-pinctrl.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2022 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ZEPHYR_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_
+#define _ZEPHYR_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_
+
+/**
+ * @brief Specify PORTx->PCR register MUX field
+ *
+ * @param port Port name ('A' to 'E')
+ * @param pin Port pin number (0 to 31)
+ * @param mux Alternate function number (0 to 7)
+ */
+#define RV32M1_MUX(port, pin, mux)              \
+	(((((port) - 'A') & 0xF) << 28) |       \
+	(((pin) & 0x3F) << 22) |                \
+	(((mux) & 0x7) << 8))
+
+#endif /* _ZEPHYR_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_ */