soc: arm: nordic_nrf: add support for Nordic nrf54l family
Add soc files for new Nordic family. Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
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12
soc/arm/nordic_nrf/nrf54l/CMakeLists.txt
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soc/arm/nordic_nrf/nrf54l/CMakeLists.txt
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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../validate_rram_partitions.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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if (CONFIG_ELV_GRTC_LFXO_ALLOWED)
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message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!")
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endif()
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@ -0,0 +1,18 @@
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# Nordic Semiconductor nRF54L15 MCU
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54L15_ENGA_CPUAPP
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config SOC
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string
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default "nrf54l15_cpuapp"
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config NUM_IRQS
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default 271
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config IEEE802154_NRF5
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default IEEE802154
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endif # SOC_NRF54L15_ENGA_CPUAPP
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soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series
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soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series
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# Nordic Semiconductor nRF54L MCU line
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NRF54LX
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rsource "Kconfig.defconfig.nrf54l*"
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config SOC_SERIES
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default "nrf54l"
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config CORTEX_M_SYSTICK
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default !NRF_GRTC_TIMER
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config CACHE_NRF_CACHE
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default y if EXTERNAL_CACHE
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endif # SOC_SERIES_NRF54LX
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soc/arm/nordic_nrf/nrf54l/Kconfig.series
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soc/arm/nordic_nrf/nrf54l/Kconfig.series
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# Nordic Semiconductor nRF54L MCU line
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NRF54LX
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bool "Nordic Semiconductor nRF54L series MCU"
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select HAS_NRFX
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select HAS_NORDIC_DRIVERS
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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select SOC_FAMILY_NRF
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help
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Enable support for nRF54L MCU series
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soc/arm/nordic_nrf/nrf54l/Kconfig.soc
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soc/arm/nordic_nrf/nrf54l/Kconfig.soc
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# Nordic Semiconductor nRF54 MCU line
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NRF54LX
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config SOC_NRF54L15
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bool "NRF54L15"
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config SOC_NRF54L15_ENGA
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bool "NRF54L15 ENGA"
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select SOC_NRF54L15
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config SOC_NRF54L15_ENGA_CPUAPP
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bool "NRF54L15 ENGA CPUAPP"
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_POWEROFF
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select SOC_NRF54L15_ENGA
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config SOC_NRF54LX_SKIP_CLOCK_CONFIG
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bool "Skip clock frequency configuration in system initialization"
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help
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With this option, the CPU clock frequency is not set during system initialization.
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The CPU runs with the default, hardware-selected frequency.
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config SOC_NRF_FORCE_CONSTLAT
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bool "Force constant-latency mode"
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help
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In constant latency mode the CPU wakeup latency and the PPI task response
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will be constant and kept at a minimum. This is secured by forcing a set
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of base resources on while in sleep. The advantage of having a constant
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and predictable latency will be at the cost of having increased power consumption.
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config SOC_NRF54L_VREG_MAIN_DCDC
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bool "NRF54L DC/DC converter."
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help
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To enable, an inductor must be connected to the DC/DC converter pin.
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config SOC_NRF54L_NORMAL_VOLTAGE_MODE
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bool "NRF54L Normal Voltage Mode."
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config SOC_NRF54L_GLITCHDET_WORKAROUND
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bool "Workaround that disables glitch detector"
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default y
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help
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Temporary workaround - disabling glitch detector to limit power consumption.
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if NRF_GRTC_TIMER
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config ELV_GRTC_LFXO_ALLOWED
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bool
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depends on NRF_GRTC_SLEEP_ALLOWED
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select EXPERIMENTAL
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help
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This feature allows using ELV mode when GRTC operates with the LFXO as
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a low-frequency clock source. The LFXO is automatically activated when
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preparing to system-off.
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WARNING! This feature is EXPERIMENTAL and may brick your device!
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endif # NRF_GRTC_TIMER
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endif # SOC_SERIES_NRF54LX
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136
soc/arm/nordic_nrf/nrf54l/soc.c
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soc/arm/nordic_nrf/nrf54l/soc.c
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Nordic Semiconductor nRF54L family processor
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*
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* This module provides routines to initialize and support board-level hardware
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* for the Nordic Semiconductor nRF54L family processor.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/init.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/cache.h>
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#include <cmsis_core.h>
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#include <hal/nrf_glitchdet.h>
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#include <hal/nrf_oscillators.h>
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#include <hal/nrf_power.h>
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#include <hal/nrf_regulators.h>
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#include <soc/nrfx_coredep.h>
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#include <system_nrf54l.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#define LFXO_NODE DT_NODELABEL(lfxo)
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#define HFXO_NODE DT_NODELABEL(hfxo)
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static int nordicsemi_nrf54l_init(void)
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{
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/* Update the SystemCoreClock global variable with current core clock
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* retrieved from hardware state.
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*/
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SystemCoreClockUpdate();
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/* Enable ICACHE */
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sys_cache_instr_enable();
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if (IS_ENABLED(CONFIG_SOC_NRF54L_GLITCHDET_WORKAROUND)) {
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nrf_glitchdet_enable_set(NRF_GLITCHDET, false);
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}
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#if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
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uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM;
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uint32_t offset_k =
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(xosc32ktrim & FICR_XOSC32KTRIM_OFFSET_Msk) >> FICR_XOSC32KTRIM_OFFSET_Pos;
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uint32_t slope_field_k =
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(xosc32ktrim & FICR_XOSC32KTRIM_SLOPE_Msk) >> FICR_XOSC32KTRIM_SLOPE_Pos;
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uint32_t slope_mask_k = FICR_XOSC32KTRIM_SLOPE_Msk >> FICR_XOSC32KTRIM_SLOPE_Pos;
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uint32_t slope_sign_k = (slope_mask_k - (slope_mask_k >> 1));
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int32_t slope_k = (int32_t)(slope_field_k ^ slope_sign_k) - (int32_t)slope_sign_k;
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/* As specified in the nRF54L15 PS:
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* CAPVALUE = round( (CAPACITANCE - 4) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9)
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* + FICR->XOSC32KTRIM.OFFSET/(2^6) );
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* where CAPACITANCE is the desired capacitor value in pF, holding any
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* value between 4 pF and 18 pF in 0.5 pF steps.
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*/
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uint32_t mid_val =
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(((DT_PROP(LFXO_NODE, load_capacitance_femtofarad) * 2UL) / 1000UL - 8UL) *
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(uint32_t)(slope_k + 392)) + (offset_k << 4UL);
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uint32_t capvalue_k = mid_val >> 10UL;
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/* Round. */
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if ((mid_val % 1024UL) >= 512UL) {
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capvalue_k++;
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}
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nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)capvalue_k);
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#elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
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nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)0);
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#endif
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#if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
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uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM;
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/* The SLOPE field is in the two's complement form, hence this special
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* handling. Ideally, it would result in just one SBFX instruction for
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* extracting the slope value, at least gcc is capable of producing such
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* output, but since the compiler apparently tries first to optimize
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* additions and subtractions, it generates slightly less than optimal
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* code.
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*/
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uint32_t slope_field =
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(xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk) >> FICR_XOSC32MTRIM_SLOPE_Pos;
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uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk >> FICR_XOSC32MTRIM_SLOPE_Pos;
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uint32_t slope_sign = (slope_mask - (slope_mask >> 1));
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int32_t slope_m = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign;
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uint32_t offset_m =
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(xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk) >> FICR_XOSC32MTRIM_OFFSET_Pos;
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/* As specified in the nRF54L15 PS:
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* CAPVALUE = (((CAPACITANCE-5.5)*(FICR->XOSC32MTRIM.SLOPE+791)) +
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* FICR->XOSC32MTRIM.OFFSET<<2)>>8;
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* where CAPACITANCE is the desired total load capacitance value in pF,
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* holding any value between 4.0 pF and 17.0 pF in 0.25 pF steps.
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*/
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uint32_t capvalue =
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(((((DT_PROP(HFXO_NODE, load_capacitance_femtofarad) * 4UL) / 1000UL) - 22UL) *
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(uint32_t)(slope_m + 791) / 4UL) + (offset_m << 2UL)) >> 8UL;
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nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
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#elif DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, external)
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nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
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#endif
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if (IS_ENABLED(CONFIG_SOC_NRF_FORCE_CONSTLAT)) {
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nrf_power_task_trigger(NRF_POWER, NRF_POWER_TASK_CONSTLAT);
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}
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if (IS_ENABLED(CONFIG_SOC_NRF54L_VREG_MAIN_DCDC)) {
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nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true);
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}
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if (IS_ENABLED(CONFIG_SOC_NRF54L_NORMAL_VOLTAGE_MODE)) {
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nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MEDIUM, false);
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}
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#if defined(CONFIG_ELV_GRTC_LFXO_ALLOWED)
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nrf_regulators_elv_mode_allow_set(NRF_REGULATORS, NRF_REGULATORS_ELV_ELVGRTCLFXO_MASK);
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#endif /* CONFIG_ELV_GRTC_LFXO_ALLOWED */
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return 0;
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}
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void arch_busy_wait(uint32_t time_us)
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{
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nrfx_coredep_delay_us(time_us);
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}
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SYS_INIT(nordicsemi_nrf54l_init, PRE_KERNEL_1, 0);
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soc/arm/nordic_nrf/nrf54l/soc.h
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soc/arm/nordic_nrf/nrf54l/soc.h
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the Nordic Semiconductor NRF54L family processors.
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*/
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#ifndef _NORDICSEMI_NRF54L_SOC_H_
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#define _NORDICSEMI_NRF54L_SOC_H_
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#define __ICACHE_PRESENT 1
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#include <soc_nrf_common.h>
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#define FLASH_PAGE_ERASE_MAX_TIME_US 8000UL
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#define FLASH_PAGE_MAX_CNT 381UL
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#endif /* _NORDICSEMI_NRF54L_SOC_H_ */
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