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soc: arm: nordic_nrf: add support for Nordic nrf54l family

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Add soc files for new Nordic family.

Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
This commit is contained in:
Witold Lukasik 2023-12-11 17:28:06 +01:00 • committed by Fabio Baltieri
commit 1d9f702260
7 changed files with 289 additions and 0 deletions
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12
soc/arm/nordic_nrf/nrf54l/CMakeLists.txt Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
soc.c
../validate_rram_partitions.c)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
if (CONFIG_ELV_GRTC_LFXO_ALLOWED)
message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!")
endif()

18
soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp Normal file
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# Nordic Semiconductor nRF54L15 MCU
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54L15_ENGA_CPUAPP
config SOC
string
default "nrf54l15_cpuapp"
config NUM_IRQS
default 271
config IEEE802154_NRF5
default IEEE802154
endif # SOC_NRF54L15_ENGA_CPUAPP

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soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series Normal file
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# Nordic Semiconductor nRF54L MCU line
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NRF54LX
rsource "Kconfig.defconfig.nrf54l*"
config SOC_SERIES
default "nrf54l"
config CORTEX_M_SYSTICK
default !NRF_GRTC_TIMER
config CACHE_NRF_CACHE
default y if EXTERNAL_CACHE
endif # SOC_SERIES_NRF54LX

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soc/arm/nordic_nrf/nrf54l/Kconfig.series Normal file
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# Nordic Semiconductor nRF54L MCU line
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NRF54LX
bool "Nordic Semiconductor nRF54L series MCU"
select HAS_NRFX
select HAS_NORDIC_DRIVERS
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select SOC_FAMILY_NRF
help
Enable support for nRF54L MCU series

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soc/arm/nordic_nrf/nrf54l/Kconfig.soc Normal file
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# Nordic Semiconductor nRF54 MCU line
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NRF54LX
config SOC_NRF54L15
bool "NRF54L15"
config SOC_NRF54L15_ENGA
bool "NRF54L15 ENGA"
select SOC_NRF54L15
config SOC_NRF54L15_ENGA_CPUAPP
bool "NRF54L15 ENGA CPUAPP"
select ARM
select ARMV8_M_DSP
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select CPU_HAS_ICACHE
select CPU_HAS_ARM_SAU
select CPU_HAS_FPU
select HAS_HW_NRF_RADIO_IEEE802154
select HAS_POWEROFF
select SOC_NRF54L15_ENGA
config SOC_NRF54LX_SKIP_CLOCK_CONFIG
bool "Skip clock frequency configuration in system initialization"
help
With this option, the CPU clock frequency is not set during system initialization.
The CPU runs with the default, hardware-selected frequency.
config SOC_NRF_FORCE_CONSTLAT
bool "Force constant-latency mode"
help
In constant latency mode the CPU wakeup latency and the PPI task response
will be constant and kept at a minimum. This is secured by forcing a set
of base resources on while in sleep. The advantage of having a constant
and predictable latency will be at the cost of having increased power consumption.
config SOC_NRF54L_VREG_MAIN_DCDC
bool "NRF54L DC/DC converter."
help
To enable, an inductor must be connected to the DC/DC converter pin.
config SOC_NRF54L_NORMAL_VOLTAGE_MODE
bool "NRF54L Normal Voltage Mode."
config SOC_NRF54L_GLITCHDET_WORKAROUND
bool "Workaround that disables glitch detector"
default y
help
Temporary workaround - disabling glitch detector to limit power consumption.
if NRF_GRTC_TIMER
config ELV_GRTC_LFXO_ALLOWED
bool
depends on NRF_GRTC_SLEEP_ALLOWED
select EXPERIMENTAL
help
This feature allows using ELV mode when GRTC operates with the LFXO as
a low-frequency clock source. The LFXO is automatically activated when
preparing to system-off.
WARNING! This feature is EXPERIMENTAL and may brick your device!
endif # NRF_GRTC_TIMER
endif # SOC_SERIES_NRF54LX

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soc/arm/nordic_nrf/nrf54l/soc.c Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Nordic Semiconductor nRF54L family processor
*
* This module provides routines to initialize and support board-level hardware
* for the Nordic Semiconductor nRF54L family processor.
*/
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <zephyr/cache.h>
#include <cmsis_core.h>
#include <hal/nrf_glitchdet.h>
#include <hal/nrf_oscillators.h>
#include <hal/nrf_power.h>
#include <hal/nrf_regulators.h>
#include <soc/nrfx_coredep.h>
#include <system_nrf54l.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#define LFXO_NODE DT_NODELABEL(lfxo)
#define HFXO_NODE DT_NODELABEL(hfxo)
static int nordicsemi_nrf54l_init(void)
{
/* Update the SystemCoreClock global variable with current core clock
* retrieved from hardware state.
*/
SystemCoreClockUpdate();
/* Enable ICACHE */
sys_cache_instr_enable();
if (IS_ENABLED(CONFIG_SOC_NRF54L_GLITCHDET_WORKAROUND)) {
nrf_glitchdet_enable_set(NRF_GLITCHDET, false);
}
#if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM;
uint32_t offset_k =
(xosc32ktrim & FICR_XOSC32KTRIM_OFFSET_Msk) >> FICR_XOSC32KTRIM_OFFSET_Pos;
uint32_t slope_field_k =
(xosc32ktrim & FICR_XOSC32KTRIM_SLOPE_Msk) >> FICR_XOSC32KTRIM_SLOPE_Pos;
uint32_t slope_mask_k = FICR_XOSC32KTRIM_SLOPE_Msk >> FICR_XOSC32KTRIM_SLOPE_Pos;
uint32_t slope_sign_k = (slope_mask_k - (slope_mask_k >> 1));
int32_t slope_k = (int32_t)(slope_field_k ^ slope_sign_k) - (int32_t)slope_sign_k;
/* As specified in the nRF54L15 PS:
* CAPVALUE = round( (CAPACITANCE - 4) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9)
* + FICR->XOSC32KTRIM.OFFSET/(2^6) );
* where CAPACITANCE is the desired capacitor value in pF, holding any
* value between 4 pF and 18 pF in 0.5 pF steps.
*/
uint32_t mid_val =
(((DT_PROP(LFXO_NODE, load_capacitance_femtofarad) * 2UL) / 1000UL - 8UL) *
(uint32_t)(slope_k + 392)) + (offset_k << 4UL);
uint32_t capvalue_k = mid_val >> 10UL;
/* Round. */
if ((mid_val % 1024UL) >= 512UL) {
capvalue_k++;
}
nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)capvalue_k);
#elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)0);
#endif
#if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM;
/* The SLOPE field is in the two's complement form, hence this special
* handling. Ideally, it would result in just one SBFX instruction for
* extracting the slope value, at least gcc is capable of producing such
* output, but since the compiler apparently tries first to optimize
* additions and subtractions, it generates slightly less than optimal
* code.
*/
uint32_t slope_field =
(xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk) >> FICR_XOSC32MTRIM_SLOPE_Pos;
uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk >> FICR_XOSC32MTRIM_SLOPE_Pos;
uint32_t slope_sign = (slope_mask - (slope_mask >> 1));
int32_t slope_m = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign;
uint32_t offset_m =
(xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk) >> FICR_XOSC32MTRIM_OFFSET_Pos;
/* As specified in the nRF54L15 PS:
* CAPVALUE = (((CAPACITANCE-5.5)*(FICR->XOSC32MTRIM.SLOPE+791)) +
* FICR->XOSC32MTRIM.OFFSET<<2)>>8;
* where CAPACITANCE is the desired total load capacitance value in pF,
* holding any value between 4.0 pF and 17.0 pF in 0.25 pF steps.
*/
uint32_t capvalue =
(((((DT_PROP(HFXO_NODE, load_capacitance_femtofarad) * 4UL) / 1000UL) - 22UL) *
(uint32_t)(slope_m + 791) / 4UL) + (offset_m << 2UL)) >> 8UL;
nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
#elif DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, external)
nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
#endif
if (IS_ENABLED(CONFIG_SOC_NRF_FORCE_CONSTLAT)) {
nrf_power_task_trigger(NRF_POWER, NRF_POWER_TASK_CONSTLAT);
}
if (IS_ENABLED(CONFIG_SOC_NRF54L_VREG_MAIN_DCDC)) {
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true);
}
if (IS_ENABLED(CONFIG_SOC_NRF54L_NORMAL_VOLTAGE_MODE)) {
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MEDIUM, false);
}
#if defined(CONFIG_ELV_GRTC_LFXO_ALLOWED)
nrf_regulators_elv_mode_allow_set(NRF_REGULATORS, NRF_REGULATORS_ELV_ELVGRTCLFXO_MASK);
#endif /* CONFIG_ELV_GRTC_LFXO_ALLOWED */
return 0;
}
void arch_busy_wait(uint32_t time_us)
{
nrfx_coredep_delay_us(time_us);
}
SYS_INIT(nordicsemi_nrf54l_init, PRE_KERNEL_1, 0);

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soc/arm/nordic_nrf/nrf54l/soc.h Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the Nordic Semiconductor NRF54L family processors.
*/
#ifndef _NORDICSEMI_NRF54L_SOC_H_
#define _NORDICSEMI_NRF54L_SOC_H_
#define __ICACHE_PRESENT 1
#include <soc_nrf_common.h>
#define FLASH_PAGE_ERASE_MAX_TIME_US 8000UL
#define FLASH_PAGE_MAX_CNT 381UL
#endif /* _NORDICSEMI_NRF54L_SOC_H_ */