michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: common: riscv-privileged: align to no SW ISR table

Browse source 
In case of no SW ISR table, `_isr_wrapper` does not exist.
Do not use it for exception handling.
Future improvements might include setting it to a user-defined handler.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This commit is contained in:
Marcin Szymczyk 2024-06-07 12:08:23 +02:00 • committed by Anas Nashif
commit 1d9907a712
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
soc/common/riscv-privileged/vector.S
View file

@ -12,7 +12,9 @@ GTEXT(__start)
/* imports */ /* imports */
GTEXT(__initialize) GTEXT(__initialize)
#if defined(CONFIG_GEN_SW_ISR_TABLE)
GTEXT(_isr_wrapper) GTEXT(_isr_wrapper)
#endif
SECTION_FUNC(vectors, __start) SECTION_FUNC(vectors, __start)
#if defined(CONFIG_RISCV_GP) #if defined(CONFIG_RISCV_GP)
@ -35,7 +37,11 @@ SECTION_FUNC(vectors, __start)
* mtvec.base must be aligned to 64 bytes (this is done using * mtvec.base must be aligned to 64 bytes (this is done using
* CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT) * CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
*/ */
#if defined(CONFIG_GEN_SW_ISR_TABLE)
la t0, _isr_wrapper la t0, _isr_wrapper
#else
add t0, zero, zero
#endif
addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */ addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
csrw mtvec, t0 csrw mtvec, t0