soc: riscv: litex: add reboot

this makes it possible to reboot a
litex SoC.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

soc/litex/litex_vexriscv/CMakeLists.txt

@@ -9,6 +9,8 @@ zephyr_sources(
     ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S
 )
 
+zephyr_sources_ifdef(CONFIG_REBOOT reboot.c)
+
 zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/litex/litex_vexriscv/Kconfig.defconfig

@@ -9,4 +9,8 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config NUM_IRQS
 	default 12
 
+config REBOOT
+	depends on DT_HAS_LITEX_SOC_CONTROLLER_ENABLED
+	default y
+
 endif # SOC_LITEX_VEXRISCV

soc/litex/litex_vexriscv/reboot.c

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 Vogl Electronic GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT litex_soc_controller
+
+#include <zephyr/kernel.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/reboot.h>
+#include <soc.h>
+
+#define LITEX_CTRL_RESET DT_INST_REG_ADDR_BY_NAME(0, reset)
+
+void sys_arch_reboot(int type)
+{
+	ARG_UNUSED(type);
+	/* SoC Reset on BIT(0)*/
+	litex_write8(BIT(0), LITEX_CTRL_RESET);
+}