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drivers/crypto/crypto_it8xxx2_sha_v2.c: implement sha v2 for it82xx2 series

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Implement a new version crypto_it8xxx2_sha_v2 driver for it82xx2 series.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is contained in:
Ruibin Chang 2024-03-27 16:57:51 +08:00 • committed by Carles Cufí
commit 1d74cb74d9
8 changed files with 393 additions and 8 deletions
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3
soc/ite/ec/common/chip_chipregs.h
View file

@ -1633,6 +1633,8 @@ struct gctrl_it8xxx2_regs {
/* 0x06: Reset Status */
#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0))
#define IT8XXX2_GCTRL_IWDTR BIT(1)
/* 0x0B: Wait Next 65K Rising */
#define IT8XXX2_GCTRL_WN65K 0x00
/* 0x10: Reset Control DMM */
#define IT8XXX2_GCTRL_UART1SD BIT(3)
#define IT8XXX2_GCTRL_UART2SD BIT(2)
@ -1652,6 +1654,7 @@ struct gctrl_it8xxx2_regs {
#define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0)
/* 0x46: Pin Multi-function Enable 3 */
#define IT8XXX2_GCTRL_SMB3PSEL BIT(6)
#define IT8XXX2_GCTRL_SRAM_CRYPTO_USED BIT(5)
/* 0x4B: ETWD and UART Control */
#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0)
/* 0x5D: RISCV ILM Configuration 0 */

5
soc/ite/ec/it8xxx2/Kconfig
View file

@ -168,6 +168,11 @@ config SOC_IT8XXX2_SHA256_HW_ACCELERATE
If we enable this config, because HW limits, the sha256 data must place in
first 4KB of RAM.
config SOC_IT8XXX2_SHA256_BLOCK_SIZE
hex
default 0x500 if SOC_IT82002_AW || SOC_IT82202_AX || SOC_IT82302_AX
default 0x200
DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash
config SOC_IT8XXX2_FLASH_SIZE_BYTES

13
soc/ite/ec/it8xxx2/linker.ld
View file

@ -65,10 +65,6 @@
#define MPU_ALIGN(region_size) . = ALIGN(4)
#endif
#ifdef CONFIG_SOC_IT8XXX2_SHA256_HW_ACCELERATE
#define SHA256_BLOCK_SIZE 0x200
#endif
#include <zephyr/linker/linker-devnull.h>
MEMORY
@ -161,7 +157,7 @@ SECTIONS
/* Pad to match allocation of block in RAM,
* maintaining code alignment against ILM */
__sha256_pad_block_start = .;
. = . + SHA256_BLOCK_SIZE;
. = . + CONFIG_SOC_IT8XXX2_SHA256_BLOCK_SIZE;
#endif
/* Specially-tagged functions in SoC sources */
KEEP(*(.__ram_code))
@ -249,10 +245,11 @@ SECTIONS
__sha256_ram_block_size = \
ABSOLUTE(. - __sha256_ram_block_start);
__sha256_ram_block_end = .;
ASSERT((__sha256_ram_block_size == SHA256_BLOCK_SIZE), \
"We need 512bytes for HW sha256 module");
ASSERT((__sha256_ram_block_size == CONFIG_SOC_IT8XXX2_SHA256_BLOCK_SIZE), \
"Not compatible ram size for HW sha256 module");
ASSERT((__sha256_ram_block_end < (RAM_BASE + 0x1000)), \
"512bytes must in SRAM first 4kbytes");
"sha256 ram block must in SRAM first 4kbytes");
ASSERT(((ABSOLUTE(__sha256_ram_block_start) & 0xfff) == \
(ABSOLUTE(__sha256_pad_block_start) & 0xfff)), \
"sha256 ram block needs the same offset with sha256 rom block");