drivers: adc: Add SAM0 ADC driver
This adds a driver for the SAM0 series ADC. Tested with /tests/drivers/adc/adc_api on SAMD21. Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This commit is contained in:
Derek Hageman
Anas Nashif
parent
9a6bbbfb69
commit
1d64a46501
9 changed files with 703 additions and 0 deletions
615
drivers/adc/adc_sam0.c
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615
drivers/adc/adc_sam0.c
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/*
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* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <adc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_sam0, CONFIG_ADC_LOG_LEVEL);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#if defined(CONFIG_SOC_SERIES_SAMD21) || defined(CONFIG_SOC_SERIES_SAMR21) || \
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defined(CONFIG_SOC_SERIES_SAMD20)
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/*
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* SAMD21 Manual 33.6.2.1: The first conversion after changing the reference
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* is invalid, so we have to discard it.
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*/
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#define ADC_SAM0_REFERENCE_GLITCH 1
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#endif
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struct adc_sam0_data {
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struct adc_context ctx;
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struct device *dev;
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u16_t *buffer;
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/*
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* Saved initial start, so we can reset the advances we've done
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* if required
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*/
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u16_t *repeat_buffer;
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#ifdef ADC_SAM0_REFERENCE_GLITCH
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u8_t reference_changed;
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#endif
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};
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struct adc_sam0_cfg {
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Adc *regs;
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#ifdef MCLK
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u32_t mclk_mask;
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u32_t gclk_mask;
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u16_t gclk_id;
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#else
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u32_t gclk;
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#endif
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u32_t freq;
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u16_t prescaler;
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void (*config_func)(struct device *dev);
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};
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#define DEV_CFG(dev) \
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((const struct adc_sam0_cfg *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct adc_sam0_data *)(dev)->driver_data)
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static void wait_synchronization(Adc *const adc)
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{
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#if defined(ADC_SYNCBUSY_MASK)
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while ((adc->SYNCBUSY.reg & ADC_SYNCBUSY_MASK) != 0) {
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}
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#else
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while ((adc->STATUS.reg & ADC_STATUS_SYNCBUSY) != 0) {
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}
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#endif
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}
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static int adc_sam0_acquisition_to_clocks(struct device *dev,
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u16_t acquisition_time)
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{
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const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
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u64_t scaled_acq;
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switch (ADC_ACQ_TIME_UNIT(acquisition_time)) {
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case ADC_ACQ_TIME_TICKS:
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if (ADC_ACQ_TIME_VALUE(acquisition_time) > 64U) {
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return -EINVAL;
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}
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return (int)ADC_ACQ_TIME_VALUE(acquisition_time) - 1;
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case ADC_ACQ_TIME_MICROSECONDS:
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scaled_acq = (u64_t)ADC_ACQ_TIME_VALUE(acquisition_time) *
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1000000U;
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break;
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case ADC_ACQ_TIME_NANOSECONDS:
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scaled_acq = (u64_t)ADC_ACQ_TIME_VALUE(acquisition_time) *
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1000U;
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break;
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default:
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return -EINVAL;
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}
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/*
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* sample_time = (sample_length+1) * (clk_adc / 2)
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* sample_length = sample_time * (2/clk_adc) - 1,
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*/
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scaled_acq *= 2U;
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scaled_acq += cfg->freq / 2U;
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scaled_acq /= cfg->freq;
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if (scaled_acq <= 1U) {
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return 0;
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}
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scaled_acq -= 1U;
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if (scaled_acq >= 64U) {
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return -EINVAL;
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}
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return (int)scaled_acq;
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}
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static int adc_sam0_channel_setup(struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
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Adc *const adc = cfg->regs;
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int retval;
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u8_t SAMPCTRL = 0;
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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retval = adc_sam0_acquisition_to_clocks(dev,
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channel_cfg->acquisition_time);
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if (retval < 0) {
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LOG_ERR("Selected ADC acquisition time is not valid");
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return retval;
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}
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SAMPCTRL |= ADC_SAMPCTRL_SAMPLEN(retval);
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}
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adc->SAMPCTRL.reg = SAMPCTRL;
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wait_synchronization(adc);
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u8_t REFCTRL;
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switch (channel_cfg->reference) {
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case ADC_REF_INTERNAL:
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#ifdef ADC_REFCTRL_REFSEL_INTREF
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REFCTRL = ADC_REFCTRL_REFSEL_INTREF | ADC_REFCTRL_REFCOMP;
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/* Enable the internal reference, defaulting to 1V */
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SUPC->VREF.bit.VREFOE = 1;
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#else
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REFCTRL = ADC_REFCTRL_REFSEL_INT1V | ADC_REFCTRL_REFCOMP;
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/* Enable the internal bandgap reference */
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SYSCTRL->VREF.bit.BGOUTEN = 1;
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#endif
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break;
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case ADC_REF_VDD_1_2:
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#ifdef ADC_REFCTRL_REFSEL_INTVCC0
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REFCTRL = ADC_REFCTRL_REFSEL_INTVCC0 | ADC_REFCTRL_REFCOMP;
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#else
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REFCTRL = ADC_REFCTRL_REFSEL_INTVCC1 | ADC_REFCTRL_REFCOMP;
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#endif
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break;
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#ifdef ADC_REFCTRL_REFSEL_INTVCC1
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case ADC_REF_VDD_1:
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REFCTRL = ADC_REFCTRL_REFSEL_INTVCC1 | ADC_REFCTRL_REFCOMP;
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break;
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#endif
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case ADC_REF_EXTERNAL0:
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REFCTRL = ADC_REFCTRL_REFSEL_AREFA;
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break;
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case ADC_REF_EXTERNAL1:
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REFCTRL = ADC_REFCTRL_REFSEL_AREFB;
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break;
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default:
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LOG_ERR("Selected reference is not valid");
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return -EINVAL;
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}
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if (adc->REFCTRL.reg != REFCTRL) {
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adc->REFCTRL.reg = REFCTRL;
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wait_synchronization(adc);
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#ifdef ADC_SAM0_REFERENCE_GLITCH
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struct adc_sam0_data *data = DEV_DATA(dev);
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data->reference_changed = 1;
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#endif
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}
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u32_t INPUTCTRL = 0;
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switch (channel_cfg->gain) {
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case ADC_GAIN_1:
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#ifdef ADC_INPUTCTRL_GAIN_1X
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INPUTCTRL = ADC_INPUTCTRL_GAIN_1X;
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#endif
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break;
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#ifdef ADC_INPUTCTRL_GAIN_DIV2
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case ADC_GAIN_1_2:
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INPUTCTRL = ADC_INPUTCTRL_GAIN_DIV2;
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break;
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#endif
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#ifdef ADC_INPUTCTRL_GAIN_2X
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case ADC_GAIN_2:
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INPUTCTRL = ADC_INPUTCTRL_GAIN_2X;
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break;
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#endif
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#ifdef ADC_INPUTCTRL_GAIN_4X
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case ADC_GAIN_4:
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INPUTCTRL = ADC_INPUTCTRL_GAIN_4X;
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break;
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#endif
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#ifdef ADC_INPUTCTRL_GAIN_8X
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case ADC_GAIN_8:
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INPUTCTRL = ADC_INPUTCTRL_GAIN_8X;
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break;
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#endif
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#ifdef ADC_INPUTCTRL_GAIN_16X
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case ADC_GAIN_16:
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INPUTCTRL = ADC_INPUTCTRL_GAIN_16X;
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break;
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#endif
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default:
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LOG_ERR("Selected ADC gain is not valid");
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return -EINVAL;
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}
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INPUTCTRL |= ADC_INPUTCTRL_MUXPOS(channel_cfg->input_positive);
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if (channel_cfg->differential) {
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INPUTCTRL |= ADC_INPUTCTRL_MUXNEG(channel_cfg->input_negative);
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#ifdef ADC_INPUTCTRL_DIFFMODE
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INPUTCTRL |= ADC_INPUTCTRL_DIFFMODE;
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#else
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adc->CTRLB.bit.DIFFMODE = 1;
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wait_synchronization(adc);
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#endif
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} else {
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INPUTCTRL |= ADC_INPUTCTRL_MUXNEG_GND;
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#ifndef ADC_INPUTCTRL_DIFFMODE
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adc->CTRLB.bit.DIFFMODE = 0;
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wait_synchronization(adc);
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#endif
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}
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adc->INPUTCTRL.reg = INPUTCTRL;
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wait_synchronization(adc);
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/* Enable references if they're selected */
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switch (channel_cfg->input_positive) {
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#ifdef ADC_INPUTCTRL_MUXPOS_TEMP_Val
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case ADC_INPUTCTRL_MUXPOS_TEMP_Val:
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SYSCTRL->VREF.bit.TSEN = 1;
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break;
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#endif
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#ifdef ADC_INPUTCTRL_MUXPOS_PTAT_Val
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case ADC_INPUTCTRL_MUXPOS_PTAT_Val:
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SUPC->VREF.bit.TSEN = 1;
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break;
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#endif
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#ifdef ADC_INPUTCTRL_MUXPOS_CTAT_Val
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case ADC_INPUTCTRL_MUXPOS_CTAT_Val:
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SUPC->VREF.bit.TSEN = 1;
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break;
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#endif
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case ADC_INPUTCTRL_MUXPOS_BANDGAP_Val:
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#ifdef ADC_REFCTRL_REFSEL_INTREF
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SUPC->VREF.bit.VREFOE = 1;
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#else
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SYSCTRL->VREF.bit.BGOUTEN = 1;
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#endif
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break;
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default:
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break;
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}
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return 0;
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}
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static void adc_sam0_start_conversion(struct device *dev)
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{
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const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
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Adc *const adc = cfg->regs;
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LOG_DBG("Starting conversion");
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adc->SWTRIG.reg = ADC_SWTRIG_START;
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/*
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* Should be safe to not synchronize here because the only things
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* that might access the ADC after this will wait for it to complete
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* (synchronize finished implicitly)
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*/
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_sam0_data *data =
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CONTAINER_OF(ctx, struct adc_sam0_data, ctx);
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adc_sam0_start_conversion(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct adc_sam0_data *data =
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CONTAINER_OF(ctx, struct adc_sam0_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static int check_buffer_size(const struct adc_sequence *sequence,
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u8_t active_channels)
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{
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size_t needed_buffer_size;
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needed_buffer_size = active_channels * sizeof(u16_t);
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if (sequence->options) {
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needed_buffer_size *= (1U + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed_buffer_size) {
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LOG_ERR("Provided buffer is too small (%u/%u)",
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sequence->buffer_size, needed_buffer_size);
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return -ENOMEM;
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}
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return 0;
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}
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static int start_read(struct device *dev, const struct adc_sequence *sequence)
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{
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const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
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struct adc_sam0_data *data = DEV_DATA(dev);
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Adc *const adc = cfg->regs;
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int error;
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if (sequence->oversampling > 10U) {
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LOG_ERR("Invalid oversampling");
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return -EINVAL;
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}
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adc->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM(sequence->oversampling);
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/* AVGCTRL is not synchronized */
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#ifdef CONFIG_SOC_SERIES_SAMD20
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/*
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* Errata: silicon revisions B and C do not perform the automatic right
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* shifts in accumulation
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*/
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if (sequence->oversampling > 4U && DSU->DID.bit.REVISION < 3) {
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adc->AVGCTRL.bit.ADJRES = sequence->oversampling - 4U;
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}
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#endif
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switch (sequence->resolution) {
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case 8:
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if (sequence->oversampling) {
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LOG_ERR("Oversampling requires 12 bit resolution");
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return -EINVAL;
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}
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adc->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_8BIT_Val;
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break;
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case 10:
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if (sequence->oversampling) {
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LOG_ERR("Oversampling requires 12 bit resolution");
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return -EINVAL;
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}
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adc->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_10BIT_Val;
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break;
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case 12:
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if (sequence->oversampling) {
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adc->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_16BIT_Val;
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} else {
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adc->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_12BIT_Val;
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}
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break;
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default:
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LOG_ERR("ADC resolution value %d is not valid",
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sequence->resolution);
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return -EINVAL;
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}
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wait_synchronization(adc);
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if (sequence->channels != 1U) {
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LOG_ERR("Channel scanning is not supported");
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return -ENOTSUP;
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}
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error = check_buffer_size(sequence, 1);
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if (error) {
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return error;
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}
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data->buffer = sequence->buffer;
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data->repeat_buffer = sequence->buffer;
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/* At this point we allow the scheduler to do other things while
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* we wait for the conversions to complete. This is provided by the
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* adc_context functions. However, the caller of this function is
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* blocked until the results are in.
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*/
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int adc_sam0_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_sam0_data *data = DEV_DATA(dev);
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int error;
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adc_context_lock(&data->ctx, false, NULL);
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error = start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static void adc_sam0_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct adc_sam0_data *data = DEV_DATA(dev);
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const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
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Adc *const adc = cfg->regs;
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u16_t result;
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adc->INTFLAG.reg = ADC_INTFLAG_MASK;
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result = (u16_t)(adc->RESULT.reg);
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#ifdef ADC_SAM0_REFERENCE_GLITCH
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if (data->reference_changed) {
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data->reference_changed = 0;
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LOG_DBG("Discarded initial conversion due to reference change");
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adc_sam0_start_conversion(dev);
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return;
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}
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#endif
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*data->buffer++ = result;
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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static int adc_sam0_init(struct device *dev)
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{
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const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
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struct adc_sam0_data *data = DEV_DATA(dev);
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Adc *const adc = cfg->regs;
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#ifdef MCLK
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GCLK->PCHCTRL[cfg->gclk_id].reg = cfg->gclk_mask | GCLK_PCHCTRL_CHEN;
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MCLK->APBDMASK.reg |= cfg->mclk_mask;
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#else
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PM->APBCMASK.bit.ADC_ = 1;
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GCLK->CLKCTRL.reg = cfg->gclk | GCLK_CLKCTRL_CLKEN;
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#endif
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#ifdef ADC_CTRLA_PRESCALER_Pos
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adc->CTRLA.reg = cfg->prescaler;
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#else
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adc->CTRLB.reg = cfg->prescaler;
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#endif
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wait_synchronization(adc);
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adc->INTENCLR.reg = ADC_INTENCLR_MASK;
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adc->INTFLAG.reg = ADC_INTFLAG_MASK;
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cfg->config_func(dev);
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adc->INTENSET.reg = ADC_INTENSET_RESRDY;
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data->dev = dev;
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#ifdef ADC_SAM0_REFERENCE_GLITCH
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data->reference_changed = 1;
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#endif
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adc->CTRLA.bit.ENABLE = 1;
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wait_synchronization(adc);
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|
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adc_context_unlock_unconditionally(&data->ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ADC_ASYNC
|
||||
static int adc_sam0_read_async(struct device *dev,
|
||||
const struct adc_sequence *sequence,
|
||||
struct k_poll_signal *async)
|
||||
{
|
||||
struct adc_sam0_data *data = DEV_DATA(dev);
|
||||
int error;
|
||||
|
||||
adc_context_lock(&data->ctx, true, async);
|
||||
error = start_read(dev, sequence);
|
||||
adc_context_release(&data->ctx, error);
|
||||
|
||||
return error;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct adc_driver_api adc_sam0_api = {
|
||||
.channel_setup = adc_sam0_channel_setup,
|
||||
.read = adc_sam0_read,
|
||||
#ifdef CONFIG_ADC_ASYNC
|
||||
.read_async = adc_sam0_read_async,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
#ifdef MCLK
|
||||
|
||||
#define ADC_SAM0_CLOCK_CONTROL(n) \
|
||||
.mclk_mask = MCLK_APBDMASK_ADC##n, \
|
||||
.gclk_mask = UTIL_CAT(GCLK_PCHCTRL_GEN_GCLK, \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_GCLK), \
|
||||
.gclk_id = ADC##n##_GCLK_ID, \
|
||||
.prescaler = UTIL_CAT(ADC_CTRLA_PRESCALER_DIV, \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_PRESCALER),
|
||||
#define ADC_SAM0_CONFIGURE(n) do { \
|
||||
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev); \
|
||||
Adc *const adc = cfg->regs; \
|
||||
u32_t comp = ((*(u32_t *)ADC##n##_FUSES_BIASCOMP_ADDR) & \
|
||||
ADC##n##_FUSES_BIASCOMP_Msk) >> \
|
||||
ADC##n##_FUSES_BIASCOMP_Pos; \
|
||||
u32_t r2r = ((*(u32_t *)ADC##n##_FUSES_BIASR2R_ADDR) & \
|
||||
ADC##n##_FUSES_BIASR2R_Msk) >> \
|
||||
ADC##n##_FUSES_BIASR2R_Pos; \
|
||||
u32_t rbuf = ((*(u32_t *)ADC##n##_FUSES_BIASREFBUF_ADDR) & \
|
||||
ADC##n##_FUSES_BIASREFBUF_Msk) >> \
|
||||
ADC##n##_FUSES_BIASREFBUF_Pos; \
|
||||
adc->CALIB.reg = ADC_CALIB_BIASCOMP(comp) | \
|
||||
ADC_CALIB_BIASR2R(r2r) | \
|
||||
ADC_CALIB_BIASREFBUF(rbuf); \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
|
||||
#define ADC_SAM0_CLOCK_CONTROL(n) \
|
||||
.gclk = UTIL_CAT(GCLK_CLKCTRL_GEN_GCLK, \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_GCLK) | \
|
||||
GCLK_CLKCTRL_ID_ADC, \
|
||||
.prescaler = UTIL_CAT(ADC_CTRLB_PRESCALER_DIV, \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_PRESCALER),
|
||||
#define ADC_SAM0_CONFIGURE(n) do { \
|
||||
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev); \
|
||||
Adc *const adc = cfg->regs; \
|
||||
/* Linearity is split across two words */ \
|
||||
u32_t lin = ((*(u32_t *)ADC_FUSES_LINEARITY_0_ADDR) & \
|
||||
ADC_FUSES_LINEARITY_0_Msk) >> \
|
||||
ADC_FUSES_LINEARITY_0_Pos; \
|
||||
lin |= (((*(u32_t *)ADC_FUSES_LINEARITY_1_ADDR) & \
|
||||
ADC_FUSES_LINEARITY_1_Msk) >> \
|
||||
ADC_FUSES_LINEARITY_1_Pos) \
|
||||
<< 4; \
|
||||
u32_t bias = ((*(u32_t *)ADC_FUSES_BIASCAL_ADDR) & \
|
||||
ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;\
|
||||
adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | \
|
||||
ADC_CALIB_LINEARITY_CAL(lin); \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define ADC_SAM0_DEVICE(n) \
|
||||
static void adc_sam0_config_##n(struct device *dev); \
|
||||
static const struct adc_sam0_cfg adc_sam_cfg_##n = { \
|
||||
.regs = (Adc *)DT_ATMEL_SAM0_ADC_ADC_##n##_BASE_ADDRESS, \
|
||||
ADC_SAM0_CLOCK_CONTROL(n) \
|
||||
.freq = UTIL_CAT(UTIL_CAT(SOC_ATMEL_SAM0_GCLK, \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_GCLK), \
|
||||
_FREQ_HZ) / \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_PRESCALER, \
|
||||
.config_func = &adc_sam0_config_##n, \
|
||||
}; \
|
||||
static struct adc_sam0_data adc_sam_data_##n = { \
|
||||
ADC_CONTEXT_INIT_TIMER(adc_sam_data_##n, ctx), \
|
||||
ADC_CONTEXT_INIT_LOCK(adc_sam_data_##n, ctx), \
|
||||
ADC_CONTEXT_INIT_SYNC(adc_sam_data_##n, ctx), \
|
||||
}; \
|
||||
DEVICE_AND_API_INIT(adc0_sam_##n, DT_ATMEL_SAM0_ADC_ADC_##n##_LABEL, \
|
||||
adc_sam0_init, &adc_sam_data_##n, &adc_sam_cfg_##n,\
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
&adc_sam0_api); \
|
||||
static void adc_sam0_config_##n(struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_ATMEL_SAM0_ADC_ADC_##n##_IRQ, \
|
||||
DT_ATMEL_SAM0_ADC_ADC_##n##_IRQ_PRIORITY, \
|
||||
adc_sam0_isr, \
|
||||
DEVICE_GET(adc0_sam_##n), \
|
||||
0); \
|
||||
irq_enable(DT_ATMEL_SAM0_ADC_ADC_##n##_IRQ); \
|
||||
ADC_SAM0_CONFIGURE(n); \
|
||||
}
|
||||
|
||||
#if DT_ATMEL_SAM0_ADC_ADC_0_BASE_ADDRESS
|
||||
ADC_SAM0_DEVICE(0);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_ADC_ADC_1_BASE_ADDRESS
|
||||
ADC_SAM0_DEVICE(1);
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue