diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c index ac74c08e93d..8e638e22439 100644 --- a/drivers/serial/uart_ns16550.c +++ b/drivers/serial/uart_ns16550.c @@ -57,12 +57,8 @@ #define UART_NS16550_DLF_ENABLED #endif -#if DT_INST_PROP(0, pcie) || \ - DT_INST_PROP(1, pcie) || \ - DT_INST_PROP(2, pcie) || \ - DT_INST_PROP(3, pcie) +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE"); -#define UART_NS16550_PCIE_ENABLED #include #endif @@ -268,7 +264,7 @@ struct uart_ns16550_device_config { #ifdef UART_NS16550_PCP_ENABLED uint32_t pcp; #endif -#ifdef UART_NS16550_PCIE_ENABLED +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) bool pcie; pcie_bdf_t pcie_bdf; pcie_id_t pcie_id; @@ -350,7 +346,7 @@ static int uart_ns16550_configure(const struct device *dev, ARG_UNUSED(dev_cfg); #ifndef UART_NS16550_ACCESS_IOPORT -#ifdef UART_NS16550_PCIE_ENABLED +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) if (dev_cfg->pcie) { struct pcie_mbar mbar; @@ -365,7 +361,7 @@ static int uart_ns16550_configure(const struct device *dev, device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size, K_MEM_CACHE_NONE); } else -#endif /* UART_NS16550_PCIE_ENABLED */ +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */ { /* Map directly from DTS */ DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); diff --git a/drivers/serial/uart_ns16550_port_x.h b/drivers/serial/uart_ns16550_port_x.h index 7d614902f89..a9940f67644 100644 --- a/drivers/serial/uart_ns16550_port_x.h +++ b/drivers/serial/uart_ns16550_port_x.h @@ -16,7 +16,7 @@ static void irq_config_func_@NUM@(const struct device *port); static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_@NUM@ = { #ifdef UART_NS16550_ACCESS_IOPORT .port = DT_INST_REG_ADDR(@NUM@), -#elif !DT_INST_PROP(@NUM@, pcie) +#elif !DT_INST_ON_BUS(@NUM@, pcie) DEVICE_MMIO_ROM_INIT(DT_DRV_INST(@NUM@)), #endif .sys_clk_freq = DT_INST_PROP(@NUM@, clock_frequency), @@ -29,7 +29,7 @@ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_@NUM@ = { .pcp = DT_INST_PROP(@NUM@, pcp), #endif -#if DT_INST_PROP(@NUM@, pcie) +#if DT_INST_ON_BUS(@NUM@, pcie) .pcie = true, .pcie_bdf = DT_INST_REG_ADDR(@NUM@), .pcie_id = DT_INST_REG_SIZE(@NUM@), @@ -71,7 +71,7 @@ static void irq_config_func_@NUM@(const struct device *dev) { ARG_UNUSED(dev); -#if DT_INST_PROP(@NUM@, pcie) +#if DT_INST_ON_BUS(@NUM@, pcie) #if DT_INST_IRQN(@NUM@) == PCIE_IRQ_DETECT /* PCI(e) with auto IRQ detection */ diff --git a/dts/bindings/serial/ns16550.yaml b/dts/bindings/serial/ns16550.yaml index bf5f1c2056c..b9f2f56ffe2 100644 --- a/dts/bindings/serial/ns16550.yaml +++ b/dts/bindings/serial/ns16550.yaml @@ -22,8 +22,3 @@ properties: type: int required: false description: divisor latch fraction (DLF, if supported) - - pcie: - type: boolean - required: false - description: attached via PCI(e) bus diff --git a/dts/x86/apollo_lake.dtsi b/dts/x86/apollo_lake.dtsi index 39d7ed8c501..25d5f845c65 100644 --- a/dts/x86/apollo_lake.dtsi +++ b/dts/x86/apollo_lake.dtsi @@ -34,25 +34,16 @@ #interrupt-cells = <3>; }; - soc { + pcie0 { + label = "PCIE_0"; #address-cells = <1>; #size-cells = <1>; - compatible = "simple-bus"; + compatible = "intel,pcie"; ranges; - vtd: vtd@fed65000 { - compatible = "intel,vt-d"; - - label = "VTD_0"; - reg = <0xfed65000 0x1000>; - - status = "disabled"; - }; - uart0: uart@c000 { compatible = "ns16550"; - pcie; reg = ; label = "UART_0"; @@ -66,7 +57,6 @@ uart1: uart@c100 { compatible = "ns16550"; - pcie; reg = ; label = "UART_1"; @@ -81,7 +71,6 @@ uart2: uart@c200 { compatible = "ns16550"; - pcie; reg = ; label = "UART_2"; @@ -96,7 +85,6 @@ uart3: uart@c300 { compatible = "ns16550"; - pcie; reg = ; label = "UART_3"; @@ -107,6 +95,22 @@ status = "okay"; current-speed = <115200>; }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vtd: vtd@fed65000 { + compatible = "intel,vt-d"; + + label = "VTD_0"; + reg = <0xfed65000 0x1000>; + + status = "disabled"; + }; i2c0: i2c@b000 { compatible = "snps,designware-i2c"; diff --git a/dts/x86/elkhart_lake.dtsi b/dts/x86/elkhart_lake.dtsi index 171405c6b5d..f323cd2bedf 100644 --- a/dts/x86/elkhart_lake.dtsi +++ b/dts/x86/elkhart_lake.dtsi @@ -34,16 +34,16 @@ #interrupt-cells = <3>; }; - soc { + pcie0 { + label = "PCIE_0"; #address-cells = <1>; #size-cells = <1>; - compatible = "simple-bus"; + compatible = "intel,pcie"; ranges; uart0: uart@f000 { compatible = "ns16550"; - pcie; reg = ; label = "UART_0"; @@ -57,7 +57,6 @@ uart1: uart@f100 { compatible = "ns16550"; - pcie; reg = ; label = "UART_1"; @@ -72,7 +71,6 @@ uart2: uart@ca00 { compatible = "ns16550"; - pcie; reg = ; label = "UART_2"; @@ -87,7 +85,6 @@ uart_pse_0: uart@8800 { compatible = "ns16550"; - pcie; reg = ; label = "UART_PSE_0"; @@ -102,7 +99,6 @@ uart_pse_1: uart@8900 { compatible = "ns16550"; - pcie; reg = ; label = "UART_PSE_1"; @@ -117,7 +113,6 @@ uart_pse_2: uart@8a00 { compatible = "ns16550"; - pcie; reg = ; label = "UART_PSE_2"; @@ -132,7 +127,6 @@ uart_pse_3: uart@8b00 { compatible = "ns16550"; - pcie; reg = ; label = "UART_PSE_3"; @@ -147,7 +141,6 @@ uart_pse_4: uart@8c00 { compatible = "ns16550"; - pcie; reg = ; label = "UART_PSE_4"; @@ -162,7 +155,6 @@ uart_pse_5: uart@8d00 { compatible = "ns16550"; - pcie; reg = ; label = "UART_PSE_5"; @@ -173,6 +165,13 @@ status = "okay"; current-speed = <115200>; }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; i2c0: i2c@a800 { compatible = "snps,designware-i2c";