From 1d2a030ee3a67137a2e9a084aac43ad134f6971a Mon Sep 17 00:00:00 2001 From: Richard Osterloh Date: Wed, 4 Sep 2019 09:43:07 +0100 Subject: [PATCH] drivers: serial: Add STM32G4X serial support Add UART driver support for STM32G4X SoC series. Signed-off-by: Richard Osterloh --- drivers/serial/Kconfig.stm32 | 4 +-- drivers/serial/uart_stm32.c | 3 +- dts/arm/st/g4/stm32g4.dtsi | 46 ++++++++++++++++++++++++++++ soc/arm/st_stm32/stm32g4/dts_fixup.h | 45 +++++++++++++++++++++++++++ soc/arm/st_stm32/stm32g4/soc.h | 6 ++++ 5 files changed, 101 insertions(+), 3 deletions(-) diff --git a/drivers/serial/Kconfig.stm32 b/drivers/serial/Kconfig.stm32 index 41ea4faaba7..1af3b85023f 100644 --- a/drivers/serial/Kconfig.stm32 +++ b/drivers/serial/Kconfig.stm32 @@ -97,7 +97,7 @@ config UART_10 Enable support for UART10 port in the driver. Say y here if you want to use UART10 device. -if SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32H7X +if SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32H7X || SOC_SERIES_STM32G4X # --- low power port 1 --- @@ -107,6 +107,6 @@ config LPUART_1 Enable support for LPUART1 port in the driver. Say y here if you want to use LPUART1 device. -endif # SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX +endif # SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G4X endif # UART_STM32 diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index e1cebdb20c1..75c20aa908f 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -818,7 +818,8 @@ STM32_UART_INIT(UART_10) #if defined(CONFIG_SOC_SERIES_STM32H7X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32L0X) || \ - defined(CONFIG_SOC_SERIES_STM32WBX) + defined(CONFIG_SOC_SERIES_STM32WBX) || \ + defined(CONFIG_SOC_SERIES_STM32G4X) #ifdef CONFIG_LPUART_1 STM32_UART_INIT(LPUART_1) #endif /* CONFIG_LPUART_1 */ diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index d64400a629f..7d8b5409eef 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -102,6 +102,52 @@ label = "GPIOG"; }; }; + + usart1: serial@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; + interrupts = <37 0>; + status = "disabled"; + label = "UART_1"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; + interrupts = <38 0>; + status = "disabled"; + label = "UART_2"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; + interrupts = <39 0>; + status = "disabled"; + label = "UART_3"; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; + interrupts = <52 0>; + status = "disabled"; + label = "UART_4"; + }; + + lpuart1: serial@40008000 { + compatible = "st,stm32-lpuart", "st,stm32-uart"; + reg = <0x40008000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>; + interrupts = <91 0>; + status = "disabled"; + label = "LPUART_1"; + }; + }; }; diff --git a/soc/arm/st_stm32/stm32g4/dts_fixup.h b/soc/arm/st_stm32/stm32g4/dts_fixup.h index 7e307c11f66..5a3d82dd384 100644 --- a/soc/arm/st_stm32/stm32g4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32g4/dts_fixup.h @@ -71,4 +71,49 @@ #define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_48001800_CLOCK_BITS #define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_48001800_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS +#define DT_UART_STM32_USART_1_HW_FLOW_CONTROL DT_ST_STM32_USART_40013800_HW_FLOW_CONTROL + +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_HW_FLOW_CONTROL DT_ST_STM32_USART_40004400_HW_FLOW_CONTROL + +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_HW_FLOW_CONTROL DT_ST_STM32_USART_40004800_HW_FLOW_CONTROL + +#define DT_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS +#define DT_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED +#define DT_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY +#define DT_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL +#define DT_UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 +#define DT_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS +#define DT_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS +#define DT_UART_STM32_UART_4_HW_FLOW_CONTROL DT_ST_STM32_UART_40004C00_HW_FLOW_CONTROL + +#define DT_UART_STM32_LPUART_1_BASE_ADDRESS DT_ST_STM32_LPUART_40008000_BASE_ADDRESS +#define DT_UART_STM32_LPUART_1_BAUD_RATE DT_ST_STM32_LPUART_40008000_CURRENT_SPEED +#define DT_UART_STM32_LPUART_1_IRQ_PRI DT_ST_STM32_LPUART_40008000_IRQ_0_PRIORITY +#define DT_UART_STM32_LPUART_1_NAME DT_ST_STM32_LPUART_40008000_LABEL +#define DT_LPUART_1_IRQ DT_ST_STM32_LPUART_40008000_IRQ_0 +#define DT_UART_STM32_LPUART_1_CLOCK_BITS DT_ST_STM32_LPUART_40008000_CLOCK_BITS +#define DT_UART_STM32_LPUART_1_CLOCK_BUS DT_ST_STM32_LPUART_40008000_CLOCK_BUS +#define DT_UART_STM32_LPUART_1_HW_FLOW_CONTROL DT_ST_STM32_LPUART_40008000_HW_FLOW_CONTROL + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h index 6ad84f03f52..09931a73c40 100644 --- a/soc/arm/st_stm32/stm32g4/soc.h +++ b/soc/arm/st_stm32/stm32g4/soc.h @@ -42,6 +42,12 @@ #ifdef CONFIG_GPIO_STM32 #include #endif + +#ifdef CONFIG_SERIAL_HAS_DRIVER +#include +#include +#endif /* CONFIG_SERIAL_HAS_DRIVER */ + #endif /* !_ASMLANGUAGE */ #endif /* _STM32G4_SOC_H_ */