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tests: benchmarks: timing_info: Enable benchmarks for riscv32.

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This patch provides support needed to get timing related
information from riscv32 based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This commit is contained in:
Adithya Baglody 2018-07-23 15:54:22 +05:30 • committed by Anas Nashif
commit 1d27b404a6
6 changed files with 125 additions and 1 deletions
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46
arch/riscv32/core/swap.S
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@ -23,6 +23,52 @@ GTEXT(_thread_entry_wrapper)
SECTION_FUNC(exception.other, __swap)
/* Make a system call to perform context switch */
#ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -__NANO_ESF_SIZEOF
sw ra, __NANO_ESF_ra_OFFSET(sp)
sw gp, __NANO_ESF_gp_OFFSET(sp)
sw tp, __NANO_ESF_tp_OFFSET(sp)
sw t0, __NANO_ESF_t0_OFFSET(sp)
sw t1, __NANO_ESF_t1_OFFSET(sp)
sw t2, __NANO_ESF_t2_OFFSET(sp)
sw t3, __NANO_ESF_t3_OFFSET(sp)
sw t4, __NANO_ESF_t4_OFFSET(sp)
sw t5, __NANO_ESF_t5_OFFSET(sp)
sw t6, __NANO_ESF_t6_OFFSET(sp)
sw a0, __NANO_ESF_a0_OFFSET(sp)
sw a1, __NANO_ESF_a1_OFFSET(sp)
sw a2, __NANO_ESF_a2_OFFSET(sp)
sw a3, __NANO_ESF_a3_OFFSET(sp)
sw a4, __NANO_ESF_a4_OFFSET(sp)
sw a5, __NANO_ESF_a5_OFFSET(sp)
sw a6, __NANO_ESF_a6_OFFSET(sp)
sw a7, __NANO_ESF_a7_OFFSET(sp)
call read_timer_start_of_swap
lw ra, __NANO_ESF_ra_OFFSET(sp)
lw gp, __NANO_ESF_gp_OFFSET(sp)
lw tp, __NANO_ESF_tp_OFFSET(sp)
lw t0, __NANO_ESF_t0_OFFSET(sp)
lw t1, __NANO_ESF_t1_OFFSET(sp)
lw t2, __NANO_ESF_t2_OFFSET(sp)
lw t3, __NANO_ESF_t3_OFFSET(sp)
lw t4, __NANO_ESF_t4_OFFSET(sp)
lw t5, __NANO_ESF_t5_OFFSET(sp)
lw t6, __NANO_ESF_t6_OFFSET(sp)
lw a0, __NANO_ESF_a0_OFFSET(sp)
lw a1, __NANO_ESF_a1_OFFSET(sp)
lw a2, __NANO_ESF_a2_OFFSET(sp)
lw a3, __NANO_ESF_a3_OFFSET(sp)
lw a4, __NANO_ESF_a4_OFFSET(sp)
lw a5, __NANO_ESF_a5_OFFSET(sp)
lw a6, __NANO_ESF_a6_OFFSET(sp)
lw a7, __NANO_ESF_a7_OFFSET(sp)
/* Release stack space */
addi sp, sp, __NANO_ESF_SIZEOF
#endif
ecall
/*