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spi_nxp_lpspi: Reintroduce fast path no configure

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Reintroduce the fast path that skips reconfiguring if we use the same
configuration, this fixes regression that causes a lot of latency at the
start of repeated transfers. Unfortuantely need to find alternative
workaround for S32K3 in order to do this instead of module reset, so
disable skipping for that platform.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder 2025-02-25 11:17:30 -06:00 • committed by Fabio Baltieri
commit 1ca895dc0e
3 changed files with 12 additions and 4 deletions
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6
drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi.c
View file

@ -210,7 +210,7 @@ static void lpspi_isr(const struct device *dev)
} }
if (spi_context_rx_len_left(ctx) == 1) { if (spi_context_rx_len_left(ctx) == 1) {
base->TCR = 0; base->TCR &= ~LPSPI_TCR_CONT_MASK;
} else if (spi_context_rx_on(ctx)) { } else if (spi_context_rx_on(ctx)) {
size_t rx_fifo_len = rx_fifo_cur_len(base); size_t rx_fifo_len = rx_fifo_cur_len(base);
size_t expected_rx_left = rx_fifo_len < ctx->rx_len ? ctx->rx_len - rx_fifo_len : 0; size_t expected_rx_left = rx_fifo_len < ctx->rx_len ? ctx->rx_len - rx_fifo_len : 0;
@ -224,7 +224,7 @@ static void lpspi_isr(const struct device *dev)
} else { } else {
spi_context_complete(ctx, dev, 0); spi_context_complete(ctx, dev, 0);
NVIC_ClearPendingIRQ(config->irqn); NVIC_ClearPendingIRQ(config->irqn);
base->TCR = 0; base->TCR &= ~LPSPI_TCR_CONT_MASK;
lpspi_wait_tx_fifo_empty(dev); lpspi_wait_tx_fifo_empty(dev);
spi_context_cs_control(ctx, false); spi_context_cs_control(ctx, false);
spi_context_release(&data->ctx, 0); spi_context_release(&data->ctx, 0);
@ -267,7 +267,7 @@ static int transceive(const struct device *dev, const struct spi_config *spi_cfg
LPSPI_Enable(base, true); LPSPI_Enable(base, true);
/* keep the chip select asserted until the end of the zephyr xfer */ /* keep the chip select asserted until the end of the zephyr xfer */
base->TCR |= LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK; base->TCR |= LPSPI_TCR_CONT_MASK;
/* tcr is written to tx fifo */ /* tcr is written to tx fifo */
lpspi_wait_tx_fifo_empty(dev); lpspi_wait_tx_fifo_empty(dev);

8
drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c
View file

@ -30,6 +30,14 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
uint32_t clock_freq; uint32_t clock_freq;
int ret; int ret;
/* fast path to avoid reconfigure */
/* TODO: S32K3 errata ERR050456 requiring module reset before every transfer,
* investigate alternative workaround so we don't have this latency for S32.
*/
if (spi_context_configured(ctx, spi_cfg) && !IS_ENABLED(CONFIG_SOC_FAMILY_NXP_S32)) {
return 0;
}
if (spi_cfg->operation & SPI_HALF_DUPLEX) { if (spi_cfg->operation & SPI_HALF_DUPLEX) {
/* the IP DOES support half duplex, need to implement driver support */ /* the IP DOES support half duplex, need to implement driver support */
LOG_ERR("Half-duplex not supported"); LOG_ERR("Half-duplex not supported");

2
drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_dma.c
View file

@ -285,7 +285,7 @@ static int transceive_dma_sync(const struct device *dev)
spi_context_cs_control(ctx, false); spi_context_cs_control(ctx, false);
base->TCR = 0; base->TCR &= ~LPSPI_TCR_CONT_MASK;
return 0; return 0;
} }