boards: arm: stm32f746g_disco: add support for FMC SDRAM
Add support for FMC SDRAM in board DTS Update board doc and yaml Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
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@ -116,6 +116,8 @@ The Zephyr stm32f746g_disco board configuration supports the following hardware
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+-----------+------------+-------------------------------------+
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| QSPI NOR | on-chip | off-chip flash |
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+-----------+------------+-------------------------------------+
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| FMC | on-chip | memc (SDRAM) |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on Zephyr porting.
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@ -147,6 +149,15 @@ configured as follows
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- LD1 : PI1
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- USB DM : PA11
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- USB DP : PA12
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- FMC SDRAM :
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- D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10
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- A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1
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- A14/A15 : PG4/PG5
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- SDNRAS/SDNCAS : PF11/PG15
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- NBL0/NBL1 : PE0/PE1
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- SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3
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System Clock
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============
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@ -38,6 +38,13 @@
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};
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};
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sdram1: sdram@c0000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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device_type = "memory";
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reg = <0xc0000000 DT_SIZE_M(16)>;
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zephyr,memory-region = "SDRAM1";
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};
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aliases {
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led0 = &green_led_1;
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sw0 = &user_button;
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@ -185,3 +192,44 @@ zephyr_udc0: &usbotg_fs {
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};
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};
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};
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&fmc {
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pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
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&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_pc3
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&fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
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&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
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&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
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&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
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&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
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&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
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&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
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&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
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&fmc_d15_pd10>;
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pinctrl-names = "default";
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status = "okay";
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sdram {
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status = "okay";
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power-up-delay = <100>;
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num-auto-refresh = <8>;
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mode-register = <0x220>;
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/*
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* Auto refresh command shall be issued every 15.625 us
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* and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
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* Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
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*/
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refresh-rate = <1667>;
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bank@0 {
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reg = <0>;
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st,sdram-control = <STM32_FMC_SDRAM_NC_8
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STM32_FMC_SDRAM_NR_12
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STM32_FMC_SDRAM_MWID_16
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STM32_FMC_SDRAM_NB_4
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STM32_FMC_SDRAM_CAS_2
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STM32_FMC_SDRAM_SDCLK_PERIOD_2
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STM32_FMC_SDRAM_RBURST_ENABLE
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STM32_FMC_SDRAM_RPIPE_0>;
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st,sdram-timing = <2 6 4 6 2 2 2>;
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};
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};
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};
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@ -19,3 +19,4 @@ supported:
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- sdhc
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- usb_device
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- kscan:touch
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- memc
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