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dts: bindings: nordic,nrf-pinctrl: remove pinctrl nordic,clock-enable

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Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-08-08 16:23:38 +02:00 • committed by Carles Cufí
commit 1c689fce18
10 changed files with 22 additions and 75 deletions
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16
boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi
View file

@ -26,12 +26,8 @@
/omit-if-no-ref/ uart135_default: uart135_default { /omit-if-no-ref/ uart135_default: uart135_default {
group1 { group1 {
psels = <NRF_PSEL(UART_TX, 1, 11)>; psels = <NRF_PSEL(UART_TX, 1, 11)>,
nordic,clock-enable; <NRF_PSEL(UART_RTS, 1, 9)>;
};
group2 {
psels = <NRF_PSEL(UART_RTS, 1, 9)>;
}; };
group3 { group3 {
@ -53,12 +49,8 @@
/omit-if-no-ref/ uart136_default: uart136_default { /omit-if-no-ref/ uart136_default: uart136_default {
group1 { group1 {
psels = <NRF_PSEL(UART_TX, 2, 6)>; psels = <NRF_PSEL(UART_TX, 2, 6)>,
nordic,clock-enable; <NRF_PSEL(UART_RTS, 2, 7)>;
};
group2 {
psels = <NRF_PSEL(UART_RTS, 2, 7)>;
}; };
group3 { group3 {

6
dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml
View file

@ -119,9 +119,3 @@ child-binding:
description: | description: |
Invert pin polarity (set the active state to low). Invert pin polarity (set the active state to low).
Only valid for PWM channel output pins. Only valid for PWM channel output pins.
nordic,clock-enable:
type: boolean
description: |
Enable clock for the pin. Only valid or required for certain
peripherals, refer to the reference manual.

1
tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
View file

@ -10,7 +10,6 @@
group1 { group1 {
psels = <NRF_PSEL(SPIM_MOSI, 2, 8)>, psels = <NRF_PSEL(SPIM_MOSI, 2, 8)>,
<NRF_PSEL(SPIM_SCK, 1, 2)>; <NRF_PSEL(SPIM_SCK, 1, 2)>;
nordic,clock-enable;
}; };
}; };

2
tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
View file

@ -9,7 +9,6 @@
group1 { group1 {
psels = <NRF_PSEL(TWIM_SDA, 2, 8)>, psels = <NRF_PSEL(TWIM_SDA, 2, 8)>,
<NRF_PSEL(TWIM_SCL, 1, 2)>; <NRF_PSEL(TWIM_SCL, 1, 2)>;
nordic,clock-enable;
}; };
}; };
@ -28,7 +27,6 @@
psels = <NRF_PSEL(TWIM_SDA, 2, 9)>, psels = <NRF_PSEL(TWIM_SDA, 2, 9)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>; <NRF_PSEL(TWIM_SCL, 1, 3)>;
bias-pull-up; bias-pull-up;
nordic,clock-enable;
}; };
}; };

16
tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi
View file

@ -8,12 +8,8 @@
spi130_default_alt: spi130_default_alt { spi130_default_alt: spi130_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 0)>, psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
<NRF_PSEL(SPIM_MOSI, 0, 8)>; <NRF_PSEL(SPIM_MOSI, 0, 8)>,
nordic,clock-enable; <NRF_PSEL(SPIM_MISO, 0, 6)>;
};
group2 {
psels = <NRF_PSEL(SPIM_MISO, 0, 6)>;
}; };
}; };
@ -29,12 +25,8 @@
spis131_default_alt: spis131_default_alt { spis131_default_alt: spis131_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIS_SCK, 0, 1)>, psels = <NRF_PSEL(SPIS_SCK, 0, 1)>,
<NRF_PSEL(SPIS_MISO, 0, 7)>; <NRF_PSEL(SPIS_MISO, 0, 7)>,
nordic,clock-enable; <NRF_PSEL(SPIS_MOSI, 0, 9)>,
};
group2 {
psels = <NRF_PSEL(SPIS_MOSI, 0, 9)>,
<NRF_PSEL(SPIS_CSN, 0, 11)>; <NRF_PSEL(SPIS_CSN, 0, 11)>;
}; };
}; };

8
tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay
View file

@ -25,12 +25,8 @@
spis131_default_alt: spis131_default_alt { spis131_default_alt: spis131_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIS_SCK, 1, 0)>, psels = <NRF_PSEL(SPIS_SCK, 1, 0)>,
<NRF_PSEL(SPIS_MISO, 1, 9)>; <NRF_PSEL(SPIS_MISO, 1, 9)>,
nordic,clock-enable; <NRF_PSEL(SPIS_MOSI, 1, 5)>,
};
group2 {
psels = <NRF_PSEL(SPIS_MOSI, 1, 5)>,
<NRF_PSEL(SPIS_CSN, 0, 11)>; <NRF_PSEL(SPIS_CSN, 0, 11)>;
}; };
}; };

16
tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
View file

@ -8,12 +8,8 @@
spi130_default_alt: spi130_default_alt { spi130_default_alt: spi130_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 0)>, psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
<NRF_PSEL(SPIM_MOSI, 0, 8)>; <NRF_PSEL(SPIM_MOSI, 0, 8)>,
nordic,clock-enable; <NRF_PSEL(SPIM_MISO, 0, 6)>;
};
group2 {
psels = <NRF_PSEL(SPIM_MISO, 0, 6)>;
}; };
}; };
@ -29,12 +25,8 @@
spis131_default_alt: spis131_default_alt { spis131_default_alt: spis131_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIS_SCK, 0, 1)>, psels = <NRF_PSEL(SPIS_SCK, 0, 1)>,
<NRF_PSEL(SPIS_MISO, 0, 7)>; <NRF_PSEL(SPIS_MISO, 0, 7)>,
nordic,clock-enable; <NRF_PSEL(SPIS_MOSI, 0, 9)>,
};
group2 {
psels = <NRF_PSEL(SPIS_MOSI, 0, 9)>,
<NRF_PSEL(SPIS_CSN, 0, 11)>; <NRF_PSEL(SPIS_CSN, 0, 11)>;
}; };
}; };

8
tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay
View file

@ -25,12 +25,8 @@
spis131_default_alt: spis131_default_alt { spis131_default_alt: spis131_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIS_SCK, 1, 0)>, psels = <NRF_PSEL(SPIS_SCK, 1, 0)>,
<NRF_PSEL(SPIS_MISO, 1, 9)>; <NRF_PSEL(SPIS_MISO, 1, 9)>,
nordic,clock-enable; <NRF_PSEL(SPIS_MOSI, 1, 5)>,
};
group2 {
psels = <NRF_PSEL(SPIS_MOSI, 1, 5)>,
<NRF_PSEL(SPIS_CSN, 0, 11)>; <NRF_PSEL(SPIS_CSN, 0, 11)>;
}; };
}; };

16
tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
View file

@ -8,12 +8,8 @@
spi130_default_alt: spi130_default_alt { spi130_default_alt: spi130_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 0)>, psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
<NRF_PSEL(SPIM_MOSI, 0, 8)>; <NRF_PSEL(SPIM_MOSI, 0, 8)>,
nordic,clock-enable; <NRF_PSEL(SPIM_MISO, 0, 6)>;
};
group2 {
psels = <NRF_PSEL(SPIM_MISO, 0, 6)>;
}; };
}; };
@ -29,12 +25,8 @@
spis131_default_alt: spis131_default_alt { spis131_default_alt: spis131_default_alt {
group1 { group1 {
psels = <NRF_PSEL(SPIS_SCK, 0, 1)>, psels = <NRF_PSEL(SPIS_SCK, 0, 1)>,
<NRF_PSEL(SPIS_MISO, 0, 7)>; <NRF_PSEL(SPIS_MISO, 0, 7)>,
nordic,clock-enable; <NRF_PSEL(SPIS_MOSI, 0, 9)>,
};
group2 {
psels = <NRF_PSEL(SPIS_MOSI, 0, 9)>,
<NRF_PSEL(SPIS_CSN, 0, 11)>; <NRF_PSEL(SPIS_CSN, 0, 11)>;
}; };
}; };

8
tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
View file

@ -8,12 +8,8 @@
spi130_default: spi130_default { spi130_default: spi130_default {
group1 { group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 0)>, psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
<NRF_PSEL(SPIM_MOSI, 0, 7)>; <NRF_PSEL(SPIM_MOSI, 0, 7)>,
nordic,clock-enable; <NRF_PSEL(SPIM_MISO, 0, 6)>;
};
group2 {
psels = <NRF_PSEL(SPIM_MISO, 0, 6)>;
}; };
}; };