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dts: atmel sam: Add pinctrl support for SAM TWI and TWIHS I2C

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Add pinctl support for the SAM TWI and TWIHS I2C devices.  We update
the TWI and TWIHS I2C bindings to have pinctrl-0 bindings that are
expected to have 2 phandles to the TWCK & TWD pinctrl nodes.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-20 04:56:00 -05:00 • committed by Kumar Gala
commit 1b0e4124da
10 changed files with 51 additions and 0 deletions
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4
dts/arm/atmel/sam3x-pinctrl.dtsi
View file

@ -10,6 +10,10 @@
soc { soc {
pinctrl@400e0e00 { pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */ /* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(twi0, twck0, a, 18, a);
DT_ATMEL_PIN(twi0, twd0, a, 17, a);
DT_ATMEL_PIN(twi1, twck1, b, 13, a);
DT_ATMEL_PIN(twi1, twd1, b, 12, a);
DT_ATMEL_PIN(uart, urxd, a, 8, a); DT_ATMEL_PIN(uart, urxd, a, 8, a);
DT_ATMEL_PIN(uart, utxd, a, 9, a); DT_ATMEL_PIN(uart, utxd, a, 9, a);
DT_ATMEL_PIN(usart0, cts0, b, 26, a); DT_ATMEL_PIN(usart0, cts0, b, 26, a);

2
dts/arm/atmel/sam3x.dtsi
View file

@ -67,6 +67,7 @@
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&pa18a_twi0_twck0 &pa17a_twi0_twd0>;
}; };
twi1: i2c@40090000 { twi1: i2c@40090000 {
@ -79,6 +80,7 @@
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&pb13a_twi1_twck1 &pb12a_twi1_twd1>;
}; };
uart: uart@400e0800 { uart: uart@400e0800 {

4
dts/arm/atmel/sam4e-pinctrl.dtsi
View file

@ -10,6 +10,10 @@
soc { soc {
pinctrl@400e0e00 { pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */ /* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(twi0, twck0, a, 4, a);
DT_ATMEL_PIN(twi0, twd0, a, 3, a);
DT_ATMEL_PIN(twi1, twck1, b, 5, a);
DT_ATMEL_PIN(twi1, twd1, b, 4, a);
DT_ATMEL_PIN(uart0, urxd0, a, 9, a); DT_ATMEL_PIN(uart0, urxd0, a, 9, a);
DT_ATMEL_PIN(uart0, utxd0, a, 10, a); DT_ATMEL_PIN(uart0, utxd0, a, 10, a);
DT_ATMEL_PIN(uart1, urxd1, a, 5, c); DT_ATMEL_PIN(uart1, urxd1, a, 5, c);

2
dts/arm/atmel/sam4e.dtsi
View file

@ -66,6 +66,7 @@
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&pa4a_twi0_twck0 &pa3a_twi0_twd0>;
}; };
twi1: i2c@400ac000 { twi1: i2c@400ac000 {
@ -78,6 +79,7 @@
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&pb5a_twi1_twck1 &pb4a_twi1_twd1>;
}; };
spi0: spi@40088000 { spi0: spi@40088000 {

4
dts/arm/atmel/sam4s-pinctrl.dtsi
View file

@ -10,6 +10,10 @@
soc { soc {
pinctrl@400e0e00 { pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */ /* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(twi0, twck0, a, 4, a);
DT_ATMEL_PIN(twi0, twd0, a, 3, a);
DT_ATMEL_PIN(twi1, twck1, b, 5, a);
DT_ATMEL_PIN(twi1, twd1, b, 4, a);
DT_ATMEL_PIN(uart0, urxd0, a, 9, a); DT_ATMEL_PIN(uart0, urxd0, a, 9, a);
DT_ATMEL_PIN(uart0, utxd0, a, 10, a); DT_ATMEL_PIN(uart0, utxd0, a, 10, a);
DT_ATMEL_PIN(uart1, urxd1, b, 2, a); DT_ATMEL_PIN(uart1, urxd1, b, 2, a);

2
dts/arm/atmel/sam4s.dtsi
View file

@ -67,6 +67,7 @@
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&pa4a_twi0_twck0 &pa3a_twi0_twd0>;
}; };
twi1: i2c@4001c000 { twi1: i2c@4001c000 {
@ -79,6 +80,7 @@
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&pb5a_twi1_twck1 &pb4a_twi1_twd1>;
}; };
spi0: spi@40008000 { spi0: spi@40008000 {

6
dts/arm/atmel/same70-pinctrl.dtsi
View file

@ -10,6 +10,12 @@
soc { soc {
pinctrl@400e0e00 { pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */ /* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(twihs0, twck0, a, 4, a);
DT_ATMEL_PIN(twihs0, twd0, a, 3, a);
DT_ATMEL_PIN(twihs1, twck1, b, 5, a);
DT_ATMEL_PIN(twihs1, twd1, b, 4, a);
DT_ATMEL_PIN(twihs2, twck2, d, 28, c);
DT_ATMEL_PIN(twihs2, twd2, d, 27, c);
DT_ATMEL_PIN(uart0, urxd0, a, 9, a); DT_ATMEL_PIN(uart0, urxd0, a, 9, a);
DT_ATMEL_PIN(uart0, utxd0, a, 10, a); DT_ATMEL_PIN(uart0, utxd0, a, 10, a);
DT_ATMEL_PIN(uart1, urxd1, a, 5, c); DT_ATMEL_PIN(uart1, urxd1, a, 5, c);

3
dts/arm/atmel/same70.dtsi
View file

@ -83,6 +83,7 @@
peripheral-id = <19>; peripheral-id = <19>;
label = "I2C_0"; label = "I2C_0";
status = "disabled"; status = "disabled";
pinctrl-0 = <&pa4a_twihs0_twck0 &pa3a_twihs0_twd0>;
}; };
twihs1: i2c@4001c000 { twihs1: i2c@4001c000 {
@ -95,6 +96,7 @@
peripheral-id = <20>; peripheral-id = <20>;
label = "I2C_1"; label = "I2C_1";
status = "disabled"; status = "disabled";
pinctrl-0 = <&pb5a_twihs1_twck1 &pb4a_twihs1_twd1>;
}; };
twihs2: i2c@40060000 { twihs2: i2c@40060000 {
@ -107,6 +109,7 @@
peripheral-id = <41>; peripheral-id = <41>;
label = "I2C_2"; label = "I2C_2";
status = "disabled"; status = "disabled";
pinctrl-0 = <&pd28c_twihs2_twck2 &pd27c_twihs2_twd2>;
}; };
spi0: spi@40008000 { spi0: spi@40008000 {

12
dts/bindings/i2c/atmel,sam-i2c-twi.yaml
View file

@ -18,3 +18,15 @@ properties:
type: int type: int
description: peripheral ID description: peripheral ID
required: true required: true
pinctrl-0:
type: phandles
required: true
description: |
PIO pin configuration for TWCK & TWD signals. We expect that
the phandles will reference pinctrl nodes. These nodes will
have a nodelabel that matches the Atmel SoC HAL defines and
be of the form p<port><pin><periph>_<inst>_<signal>.
For example the I2C on SAM3x would be
pinctrl-0 = <&pa18a_twi0_twck0 &pa17a_twi0_twd0>;

12
dts/bindings/i2c/atmel,sam-i2c-twihs.yaml
View file

@ -18,3 +18,15 @@ properties:
type: int type: int
description: peripheral ID description: peripheral ID
required: true required: true
pinctrl-0:
type: phandles
required: true
description: |
PIO pin configuration for TWCK & TWD signals. We expect that
the phandles will reference pinctrl nodes. These nodes will
have a nodelabel that matches the Atmel SoC HAL defines and
be of the form p<port><pin><periph>_<inst>_<signal>.
For example the I2C on SAME7x would be
pinctrl-0 = <&pa4a_twihs0_twck0 &pa3a_twihs0_twd0>;