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soc: intel_adsp_cavs25: Fix linker section overlap, support !COHERENCE

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The alignment on .bss was coming out wrong.  The ". = ALIGN(4096);"
statement was being ignored, somewhat inexplicably.  This resulted in
the bss symbols being assigned corret-seeming, non-overlapping
addresses.  But it overlapped the page-sized padding at the end of
.data.

As it turns out, the rimage format (not the linker or Zephyr) requires
page-sized sections to copy, and the bootloader code does that copy by
writing to the CACHED mapping of the memory (.bss is, like .data,
uncached/coherent by default).  So at runtime the CPU was running in a
context where the cache was populated with "booby trap" data at the
start of .bss.  True .bss access would hit the memory uncached and see
the "correct" value, but at arbitrary times during execution lines
would be flushed out of L1 cache on top of it.

Oops.  This was found by accident, actually, as routine changes to the
linker script to correctly support the case where KERNEL_COHERENCE=n
(i.e. put everything in the cached mapping and nothing in uncached)
suddenly hit rimage failures because of the overlap.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-08-25 16:16:56 -06:00 • committed by Anas Nashif
commit 1ac3e94f7a
1 changed files with 24 additions and 3 deletions
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27
soc/xtensa/intel_adsp/cavs_v25/linker.ld
View file

@ -43,8 +43,15 @@ PROVIDE(_MemErrorHandler = 0x00000000);
* 512MB of unused data into the output file!)
*
*/
#ifdef CONFIG_KERNEL_COHERENCE
#define SEGSTART_CACHED (ALIGN(64) | 0x20000000)
#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)
#else
#define SEGSTART_CACHED /**/
#define SEGSTART_UNCACHED /**/
#define ucram ram
#define ucram_phdr ram_phdr
#endif
MEMORY
{
@ -114,9 +121,11 @@ MEMORY
ram :
org = RAM_BASE,
len = RAM_SIZE
#ifdef CONFIG_KERNEL_COHERENCE
ucram :
org = RAM_BASE - 0x20000000,
len = RAM_SIZE
#endif
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST :
org = IDT_BASE,
@ -174,7 +183,9 @@ PHDRS
vector_double_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
ram_phdr PT_LOAD;
#ifdef CONFIG_KERNEL_COHERENCE
ucram_phdr PT_LOAD;
#endif
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
@ -501,11 +512,13 @@ SECTIONS
_lit4_end = ABSOLUTE(.);
} >ram :ram_phdr
#ifdef CONFIG_KERNEL_COHERENCE
/* These values need to change in our scheme, where the common-ram
* sections need to be linked in safe/uncached memory but common-rom
* wants to use the cache
*/
. = SEGSTART_UNCACHED;
#endif
#undef RAMABLE_REGION
#undef ROMABLE_REGION
@ -553,9 +566,9 @@ SECTIONS
. = ALIGN(4096);
.bss SEGSTART_UNCACHED (NOLOAD) :
.bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)
{
_bss_start = ABSOLUTE(.);
_bss_start = .;
*(.dynsbss)
*(.sbss)
*(.sbss.*)
@ -570,18 +583,24 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_bss_end = ABSOLUTE(.);
_bss_end = .;
} >ucram :ucram_phdr
#ifdef CONFIG_KERNEL_COHERENCE
. = SEGSTART_UNCACHED;
#endif
_end = ALIGN(8);
PROVIDE(end = ALIGN(8));
/* Re-adjust to the upper mapping for the final symbols below */
#ifdef CONFIG_KERNEL_COHERENCE
. = SEGSTART_CACHED;
#endif
__stack = L2_SRAM_BASE + L2_SRAM_SIZE;
#ifdef CONFIG_KERNEL_COHERENCE
. = SEGSTART_UNCACHED;
#endif
/* dma buffers */
.lpbuf (NOLOAD): ALIGN(4)
@ -592,7 +611,9 @@ SECTIONS
} >LP_SRAM_REGION
. = L2_SRAM_BASE + L2_SRAM_SIZE;
#ifdef CONFIG_KERNEL_COHERENCE
. = SEGSTART_UNCACHED;
#endif
_heap_sentry = .;
.comment 0 : { *(.comment) }