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arch: arm: cortex_m: fix D-Cache reset with CONFIG_INIT_ARCH_HW_AT_BOOT

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On reset we do not know what is the status of the D-Cache, nor its
content.

If it is disabled, do not try to clean it, as it might contains random
data for random addresses, and this might just create a bus fault.
Invalidating it is enough.

If it is enabled, it means its content is not random.
SCB_InvalidateDCache() will clean it, invalidate it and disable it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2021-05-13 15:29:06 +02:00 • committed by Kumar Gala
commit 1a583e44ba
1 changed files with 11 additions and 3 deletions
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14
arch/arm/core/aarch32/cortex_m/scb.c
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@ -93,9 +93,17 @@ void z_arm_init_arch_hw_at_boot(void)
}
#if defined(CONFIG_CPU_CORTEX_M7)
/* Reset Cache settings */
SCB_CleanInvalidateDCache();
SCB_DisableDCache();
/* Reset D-Cache settings. If the D-Cache was enabled,
* SCB_DisableDCache() takes care of cleaning and invalidating it.
* If it was already disabled, just call SCB_InvalidateDCache() to
* reset it to a known clean state.
*/
if (SCB->CCR & SCB_CCR_DC_Msk) {
SCB_DisableDCache();
} else {
SCB_InvalidateDCache();
}
/* Reset I-Cache settings. */
SCB_DisableICache();
#endif /* CONFIG_CPU_CORTEX_M7 */