boards: riscv: Add Microchip mpfs_icicle board

Adding board support for Microchip's PolarFire SoC Icicle Kit.

Signed-off-by: Peter McShane <peter.mcshane@microchip.com>

boards/riscv/mpfs_icicle/CMakeLists.txt

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)

boards/riscv/mpfs_icicle/Kconfig.board

@@ -0,0 +1,9 @@
+# Copyright (c) 2021-2022 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MPFS_ICICLE
+	bool "Microsemi PolarFire SoC ICICLE kit"
+	depends on SOC_MPFS
+	select 64BIT
+	select SCHED_IPI_SUPPORTED
+	select CPU_HAS_FPU_DOUBLE_PRECISION

boards/riscv/mpfs_icicle/Kconfig.defconfig

@@ -0,0 +1,6 @@
+# Copyright (c) 2020-2021 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD
+	default "mpfs_icicle"
+	depends on BOARD_MPFS_ICICLE

boards/riscv/mpfs_icicle/board.cmake

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS renode)
+set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs250t.resc)

boards/riscv/mpfs_icicle/doc/index.rst

@@ -0,0 +1,66 @@
+.. _mpfs_icicle:
+
+Microchip mpfs_icicle
+#####################
+
+Overview
+********
+
+The Microchip mpfs_icicle board is a PolarFire SoC FPGA based development board with a Microchip MPFS250T fpga device.
+The E51 RISC-V CPU can be deployed on the mpfs_icicle board.
+More information can be found on the `Microchip website <https://www.microchip.com/en-us/product/MPFS250T>`_.
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``mpfs_icicle`` board configuration can be built as usual
+(see :ref:`build_an_application`):
+
+.. zephyr-app-commands::
+   :board: mpfs_icicle
+   :goals: build
+
+
+Flashing
+========
+
+In order to upload the application to the device, you'll need OpenOCD and GDB
+with RISC-V support.
+You can get them as a part of SoftConsole SDK.
+Download and installation instructions can be found on
+`Microchip's SoftConsole website
+<https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/programming-and-debug/softconsole>`_.
+
+With the necessary tools installed, you can connect to the board using OpenOCD.
+To establish an OpenOCD connection run:
+
+.. code-block:: bash
+
+   sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
+   <softconsole_path>/openocd/bin/openocd  --file \
+   <softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
+
+
+Leave it running, and in a different terminal, use GDB to upload the binary to
+the board. You can use the RISC-V GDB from a toolchain delivered with
+SoftConsole SDK.
+
+Here is the GDB terminal command to connect to the device
+and load the binary:
+
+.. code-block:: console
+
+   <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
+   -ex "target extended-remote localhost:3333" \
+   -ex "set mem inaccessible-by-default off" \
+   -ex "set arch riscv:rv64" \
+   -ex "set riscv use_compressed_breakpoints no" \
+   -ex "load" <path_to_executable>
+
+Debugging
+=========
+
+Refer to the detailed overview of :ref:`application_debugging`.

boards/riscv/mpfs_icicle/mpfs_icicle.dts

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020-2021 Microchip Technology Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <mpfs-icicle.dtsi>
+
+/ {
+	model = "Microchip PolarFire-SoC Icicle Kit";
+	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+	aliases {
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/riscv/mpfs_icicle/mpfs_icicle.yaml

@@ -0,0 +1,11 @@
+identifier: mpfs_icicle
+name: Microchip PolarFire ICICLE kit
+type: mcu
+arch: riscv64
+toolchain:
+  - zephyr
+ram: 3840
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/riscv/mpfs_icicle/mpfs_icicle_ddr.overlay

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2020-2021 Microchip Technology Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sram = &sram1;
+	};
+};

boards/riscv/mpfs_icicle/mpfs_icicle_defconfig

@@ -0,0 +1,23 @@
+# Copyright (c) 2020-2021 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_RISCV64_MIV=y
+CONFIG_SOC_MPFS=y
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_BOARD_MPFS_ICICLE=y
+CONFIG_NO_OPTIMIZATIONS=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550=y
+CONFIG_RISCV_SOC_INTERRUPT_INIT=y
+CONFIG_RISCV_HAS_PLIC=y
+CONFIG_PLIC=y
+CONFIG_RISCV_MACHINE_TIMER=y
+CONFIG_GPIO=n
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_FPU=n

boards/riscv/mpfs_icicle/support/mpfs250t.resc

@@ -0,0 +1,17 @@
+:name: MPFS-ICICLE-KIT
+:description: This script is prepared to run Zephyr on a PolarFire SoC Icicle Kit RISC-V board.
+
+$name?="MPFS-ICICLE-KIT"
+
+using sysbus
+mach create $name
+machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl
+
+showAnalyzer mmuart0
+e51 PerformanceInMips 80
+
+macro reset
+"""
+    sysbus LoadELF $bin
+"""
+runMacro $reset