From 19e7e85cef1ae257c0191cf8e94bc20a2c50ce06 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Thu, 29 Apr 2021 09:36:02 +0200 Subject: [PATCH] boards: nucleo_l4r5zi: Use dts for clocks configuration Convert board to use of device tree for clocks configuration. Signed-off-by: Alexandre Bourdiol --- boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts | 22 ++++++++++++ .../arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig | 36 +------------------ 2 files changed, 23 insertions(+), 35 deletions(-) diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts b/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts index b105af3a87f..3f0eef07295 100644 --- a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts +++ b/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts @@ -54,6 +54,28 @@ }; }; +&clk_hsi { + status = "okay"; +}; + +&pll { + div-m = <4>; + mul-n = <40>; + div-p = <7>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; current-speed = <115200>; diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig b/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig index cb4a0832496..8719d09a178 100644 --- a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig +++ b/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig @@ -3,15 +3,6 @@ CONFIG_SOC_SERIES_STM32L4X=y CONFIG_SOC_STM32L4R5XX=y -# 120MHz system clock only in 'boost power' mode. DM00310109, section -# 5.1.7 states that the R1MODE bit must be cleared before system can -# be 120MHz. This requires an update to the stm32 clock control -# driver, so default to 80MHz until then. -# CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 - -# 80MHz system clock in 'normal power' mode -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 - # enable uart driver CONFIG_SERIAL=y @@ -21,34 +12,9 @@ CONFIG_PINMUX=y # Enable GPIO CONFIG_GPIO=y -# Clock Configuration +# Enable Clocks CONFIG_CLOCK_CONTROL=y -# Use PLLCLK for SYSCLK -CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y - -# Use HSI (16MHz) to feed into PLL -CONFIG_CLOCK_STM32_PLL_SRC_HSI=y - -CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 -CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7 -CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2 -CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 - -# Produce 80MHz clock at PLLCLK output -CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=40 - -# Comment out above and uncomment below for 120MHz. Note that you -# must have configured the mcu for boost power mode. -# CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=60 - -# Produce Max (80MHz or 120MHz) HCLK -CONFIG_CLOCK_STM32_AHB_PRESCALER=1 - -# Produce Max (80MHz or 120MHz) APB1 clocks and APB2 clocks -CONFIG_CLOCK_STM32_APB1_PRESCALER=1 -CONFIG_CLOCK_STM32_APB2_PRESCALER=1 - # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y