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drivers: dma: siwx91x: Bug fix for regular DMA transfers

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Addressed an issue where regular/non-scatter-gather DMA
transfers were not explicitly using the primary DMA descriptor
structure. This ensures a smooth regular DMA transfer after
any scatter gather transfer.

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
This commit is contained in:
Sai Santhosh Malae 2025-04-18 11:37:26 +05:30 • committed by Benjamin Cabé
commit 19e4c56e23
1 changed files with 3 additions and 0 deletions
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3
drivers/dma/dma_silabs_siwx91x.c
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@ -343,6 +343,9 @@ static int siwx91x_direct_chan_config(const struct device *dev, RSI_UDMA_HANDLE_
channel_control.dstInc = UDMA_DST_INC_NONE; channel_control.dstInc = UDMA_DST_INC_NONE;
} }
/* Clear the CHNL_PRI_ALT_CLR to use primary DMA descriptor structure */
sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_PRI_ALT_CLR);
status = UDMAx_ChannelConfigure(&udma_resources, (uint8_t)channel, status = UDMAx_ChannelConfigure(&udma_resources, (uint8_t)channel,
config->head_block->source_address, config->head_block->source_address,
config->head_block->dest_address, config->head_block->dest_address,