From 19da4ee3797608238e72431ce1ad4fcf3afbecb5 Mon Sep 17 00:00:00 2001
From: Huang Qi <757509347@qq.com>
Date: Thu, 12 Sep 2019 12:07:16 +0000
Subject: [PATCH] arch: riscv: Add simple wrokaround to boot multicore system

Just boot master core, halt others

Signed-off-by: Huang Qi <757509347@qq.com>
---
 arch/riscv/core/reset.S | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/core/reset.S b/arch/riscv/core/reset.S
index 9b1d97887ab..522426809cc 100644
--- a/arch/riscv/core/reset.S
+++ b/arch/riscv/core/reset.S
@@ -31,6 +31,16 @@ SECTION_FUNC(reset, __reset)
  * the C domain
  */
 SECTION_FUNC(TEXT, __initialize)
+	/*
+	 * This will boot master core, just halt other cores.
+	 * Note: need to be updated for complete SMP support
+	 */
+	csrr a0, mhartid
+	beqz a0, boot_master_core
+	wfi
+
+boot_master_core:
+
 #ifdef CONFIG_INIT_STACKS
 	/* Pre-populate all bytes in _interrupt_stack with 0xAA */
 	la t0, _interrupt_stack