driver: clock: npcx: add a option to generate LFCLK via XTSOC

This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>

drivers/clock_control/Kconfig.npcx

@@ -8,3 +8,12 @@ config CLOCK_CONTROL_NPCX
 	depends on SOC_FAMILY_NPCX
 	help
 	  Enable support for NPCX clock controller driver.
+
+config CLOCK_CONTROL_NPCX_EXTERNAL_SRC
+	bool "Generate LFCLK by on-chip Crystal Oscillator"
+	depends on CLOCK_CONTROL_NPCX
+	help
+	  When this option is enabled, the internal 32.768 KHz clock (LFCLK)
+	  is generated by the on-chip Crystal Oscillator (XTOSC).
+	  This includes an on-chip oscillator, to which an external crystal
+	  and the related passive components are connected.

drivers/clock_control/clock_control_npcx.c

@@ -176,6 +176,10 @@ static int npcx_clock_control_init(const struct device *dev)
 	struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev);
 	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
 
+	if (IS_ENABLED(CONFIG_CLOCK_CONTROL_NPCX_EXTERNAL_SRC)) {
+		inst_cdcg->LFCGCTL2 |= BIT(NPCX_LFCGCTL2_XT_OSC_SL_EN);
+	}
+
 	/*
 	 * Resetting the OFMCLK (even to the same value) will make the clock
 	 * unstable for a little which can affect peripheral communication like

soc/arm/nuvoton_npcx/common/reg/reg_def.h

@@ -98,6 +98,8 @@ struct cdcg_reg {
 #define NPCX_HFCGCTRL_LOCK                    2
 #define NPCX_HFCGCTRL_CLK_CHNG                7
 
+#define NPCX_LFCGCTL2_XT_OSC_SL_EN            6
+
 /*
  * Power Management Controller (PMC) device registers
  */