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driver: clock: npcx: add a option to generate LFCLK via XTSOC

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This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit is contained in:
Jun Lin 2021-07-12 11:41:37 +08:00 • committed by Anas Nashif
commit 1974ea97a4
3 changed files with 15 additions and 0 deletions
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9
drivers/clock_control/Kconfig.npcx
View file

@ -8,3 +8,12 @@ config CLOCK_CONTROL_NPCX
depends on SOC_FAMILY_NPCX depends on SOC_FAMILY_NPCX
help help
Enable support for NPCX clock controller driver. Enable support for NPCX clock controller driver.
config CLOCK_CONTROL_NPCX_EXTERNAL_SRC
bool "Generate LFCLK by on-chip Crystal Oscillator"
depends on CLOCK_CONTROL_NPCX
help
When this option is enabled, the internal 32.768 KHz clock (LFCLK)
is generated by the on-chip Crystal Oscillator (XTOSC).
This includes an on-chip oscillator, to which an external crystal
and the related passive components are connected.

4
drivers/clock_control/clock_control_npcx.c
View file

@ -176,6 +176,10 @@ static int npcx_clock_control_init(const struct device *dev)
struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev); struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev);
const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc; const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
if (IS_ENABLED(CONFIG_CLOCK_CONTROL_NPCX_EXTERNAL_SRC)) {
inst_cdcg->LFCGCTL2 |= BIT(NPCX_LFCGCTL2_XT_OSC_SL_EN);
}
/* /*
* Resetting the OFMCLK (even to the same value) will make the clock * Resetting the OFMCLK (even to the same value) will make the clock
* unstable for a little which can affect peripheral communication like * unstable for a little which can affect peripheral communication like

2
soc/arm/nuvoton_npcx/common/reg/reg_def.h
View file

@ -98,6 +98,8 @@ struct cdcg_reg {
#define NPCX_HFCGCTRL_LOCK 2 #define NPCX_HFCGCTRL_LOCK 2
#define NPCX_HFCGCTRL_CLK_CHNG 7 #define NPCX_HFCGCTRL_CLK_CHNG 7
#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
/* /*
* Power Management Controller (PMC) device registers * Power Management Controller (PMC) device registers
*/ */