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arm: fix early boot on Cortex-M0 with init stack

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The assembler was passed immediate values that are too large for the
limited Cortex-M0 thumb assembly. Load values in registers instead of
using immediate values.

Change-Id: Ib5541c92dea03e0efb1b88ab91eeb408d151a71b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This commit is contained in:
Benjamin Walsh 2016-11-23 16:15:52 -05:00 • committed by Anas Nashif
commit 194f45cc66
1 changed files with 3 additions and 2 deletions
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5
arch/arm/core/cortex_m/reset.S
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@ -81,7 +81,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
#ifdef CONFIG_INIT_STACKS #ifdef CONFIG_INIT_STACKS
ldr r0, =_interrupt_stack ldr r0, =_interrupt_stack
mov r1, #0xaa ldr r1, =0xaa
ldr r2, =CONFIG_ISR_STACK_SIZE ldr r2, =CONFIG_ISR_STACK_SIZE
bl memset bl memset
#endif #endif
@ -91,7 +91,8 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
* gets set to _interrupt_stack during nanoInit(). * gets set to _interrupt_stack during nanoInit().
*/ */
ldr r0, =_interrupt_stack ldr r0, =_interrupt_stack
adds r0, r0, CONFIG_ISR_STACK_SIZE ldr r1, =CONFIG_ISR_STACK_SIZE
adds r0, r0, r1
msr PSP, r0 msr PSP, r0
movs.n r0, #2 /* switch to using PSP (bit1 of CONTROL reg) */ movs.n r0, #2 /* switch to using PSP (bit1 of CONTROL reg) */
msr CONTROL, r0 msr CONTROL, r0