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arm: add CPU_CORTEX_M_HAS_BASEPRI kconfig flag

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Use it to flag which CPUs can do zero latency interrupts, which depend
on being able to lock up to a specific interrupt priority.

Change-Id: I09f71366ea1d05486e38c513a09abc270884879f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This commit is contained in:
Benjamin Walsh 2016-12-12 16:20:43 -05:00 • committed by Maureen Helm
commit 194a2e3a12
1 changed files with 10 additions and 0 deletions
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10
arch/arm/core/cortex_m/Kconfig
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@ -45,6 +45,13 @@ config ISA_THUMB2
technology is featured in the processor, and in all ARMv7
architecture-based processors.
config CPU_CORTEX_M_HAS_BASEPRI
bool
# Omit prompt to signify "hidden" option
default n
help
This option signifies the CPU has the BASEPRI register.
config CPU_CORTEX_M0_M0PLUS
bool
# Omit prompt to signify "hidden" option
@ -60,6 +67,7 @@ config CPU_CORTEX_M3_M4
default n
select ATOMIC_OPERATIONS_BUILTIN
select ISA_THUMB2
select CPU_CORTEX_M_HAS_BASEPRI
help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
@ -97,6 +105,7 @@ config CPU_CORTEX_M7
default n
select ATOMIC_OPERATIONS_BUILTIN
select ISA_THUMB2
select CPU_CORTEX_M_HAS_BASEPRI
help
This option signifies the use of a Cortex-M7 CPU
@ -246,6 +255,7 @@ config ZERO_LATENCY_IRQS
bool
prompt "Enable zero-latency interrupts"
default n
depends on CPU_CORTEX_M_HAS_BASEPRI
help
Interrupt locking is done by setting exception masking to priority
one, thus allowing exception of priority zero to still come in. By