drivers: pinctrl: max32: fix correct configuring drive strength
This commit fixes configuring pin drive strength in pinctrl driver. Previously, there was a mismatch while filling pincfg and checking pincfg drive strength field. This fix simplifies the operation and avoids gpio driver header dependency. Signed-off-by: Mert Ekren <mert.ekren@analog.com> Co-Authored-By: Sadik Ozer <sadik.ozer@analog.com>
This commit is contained in:
parent
9dc0af55e2
commit
193eeaef0c
2 changed files with 2 additions and 15 deletions
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@ -5,7 +5,6 @@
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*/
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#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
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#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <gpio.h>
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@ -67,20 +66,7 @@ static int pinctrl_configure_pin(pinctrl_soc_pin_t soc_pin)
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gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIO;
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}
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switch (pincfg & MAX32_GPIO_DRV_STRENGTH_MASK) {
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case MAX32_GPIO_DRV_STRENGTH_1:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_1;
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break;
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case MAX32_GPIO_DRV_STRENGTH_2:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_2;
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break;
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case MAX32_GPIO_DRV_STRENGTH_3:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_3;
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break;
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default:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_0;
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break;
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}
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gpio_cfg.drvstr = (pincfg >> MAX32_DRV_STRENGTH_SHIFT) & MAX32_DRV_STRENGTH_MASK;
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if (MXC_GPIO_Config(&gpio_cfg) != 0) {
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return -ENOTSUP;
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@ -63,5 +63,6 @@
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#define MAX32_POWER_SOURCE_SHIFT 0x04
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#define MAX32_OUTPUT_HIGH_SHIFT 0x05
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#define MAX32_DRV_STRENGTH_SHIFT 0x06 /* 2 bits */
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#define MAX32_DRV_STRENGTH_MASK 0x03
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_ */
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