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Remove references to Cortex-M0

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The Cortex-M0 processor is not supported.

Change-Id: I3ada6615a8b41eb318f80edb13947f70459c761b
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This commit is contained in:
Peter Mitsis 2015-06-10 15:27:42 -04:00 • committed by Anas Nashif
commit 192a316ef4
2 changed files with 1 additions and 56 deletions
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53
include/arch/arm/CortexM/memory_map-m0.h
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@ -1,53 +0,0 @@
/* memory_map-m0.h - ARM CORTEX-M0 memory map */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This module contains definitions for the memory map parts specific to the
CORTEX-M0 series of processors. It is included by nanokernel/ARM/memory_map.h
*/
#ifndef _MEMORY_MAP_M0__H_
#define _MEMORY_MAP_M0__H_
/* 0xe0000000 -> 0xe00fffff: private peripheral bus [1MB] */
#define _PPB_INT_BASE_ADDR (_EDEV_END_ADDR + 1)
#define _PPB_INT_SCS (_PPB_INT_BASE_ADDR + KB(56))
#define _PPB_INT_END_ADDR (_PPB_INT_BASE_ADDR + MB(1) - 1)
/* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB] */
#define _SYSTEM_BASE_ADDR (_PPB_INT_END_ADDR + 1)
#define _SYSTEM_END_ADDR 0xffffffff
#endif /* _MEMORY_MAP_M0__H_ */

4
include/arch/arm/CortexM/memory_map.h
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@ -70,12 +70,10 @@ processors.
#define _EDEV_BASE_ADDR (_ERAM_END_ADDR + 1) #define _EDEV_BASE_ADDR (_ERAM_END_ADDR + 1)
#define _EDEV_END_ADDR (_EDEV_BASE_ADDR + GB(1) - 1) #define _EDEV_END_ADDR (_EDEV_BASE_ADDR + GB(1) - 1)
/* 0xe0000000 -> 0xffffffff is different between M3 and M0 */ /* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
#if defined(CONFIG_CPU_CORTEX_M3_M4) #if defined(CONFIG_CPU_CORTEX_M3_M4)
#include <arch/arm/CortexM/memory_map-m3-m4.h> #include <arch/arm/CortexM/memory_map-m3-m4.h>
#elif defined(CONFIG_CPU_CORTEXM0)
#include <arch/arm/CortexM/memory_map-m0.h>
#else #else
#error Unknown CPU #error Unknown CPU
#endif #endif