michaelh/zephyr
1
0
Fork 0
Code Releases Activity

Rename VXMICRO_ARCH_x86 -> CONFIG_X86_32

Browse source 
Change-Id: Ie1bcfebce1db838ea994cb3626396ea032225830
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2015-06-05 22:26:24 -04:00
commit 191fc279ce
19 changed files with 29 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

2
arch/x86/include/asm_inline.h
View file

@ -33,7 +33,7 @@
#ifndef _ASM_INLINE_H #ifndef _ASM_INLINE_H
#define _ASM_INLINE_H #define _ASM_INLINE_H
#if !defined(VXMICRO_ARCH_x86) #if !defined(CONFIG_X86_32)
#error The arch/x86/include/asm_inline.h is only for x86 architecture #error The arch/x86/include/asm_inline.h is only for x86 architecture
#endif #endif

10
doc/doxygen/irq_test_common_commented.h
View file

@ -40,7 +40,7 @@ Interrupt stuff, abstracted across CPU architectures.
#define _IRQ_TEST_COMMON__H_ #define _IRQ_TEST_COMMON__H_
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3 #define IRQ_PRIORITY 3
#elif defined(VXMICRO_ARCH_arm) #elif defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEXM)
@ -58,7 +58,7 @@ Interrupt stuff, abstracted across CPU architectures.
#error NUM_SW_IRQS only supports 1 or 2 IRQs #error NUM_SW_IRQS only supports 1 or 2 IRQs
#endif #endif
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
static NANO_CPU_INT_STUB_DECL(nanoIntStub1); static NANO_CPU_INT_STUB_DECL(nanoIntStub1);
#if NUM_SW_IRQS >= 2 #if NUM_SW_IRQS >= 2
static NANO_CPU_INT_STUB_DECL(nanoIntStub2); static NANO_CPU_INT_STUB_DECL(nanoIntStub2);
@ -71,7 +71,7 @@ typedef void (*vvfn)(void);
/*! Declares a void-void_pointer function pointer to test the ISR. */ /*! Declares a void-void_pointer function pointer to test the ISR. */
typedef void (*vvpfn)(void *); typedef void (*vvpfn)(void *);
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
/* /*
* Opcode for generating a software interrupt. The ISR associated with each * Opcode for generating a software interrupt. The ISR associated with each
* of these software interrupts will call either nano_isr_lifo_put() or * of these software interrupts will call either nano_isr_lifo_put() or
@ -134,7 +134,7 @@ static int initIRQ
struct isrInitInfo *i struct isrInitInfo *i
) )
{ {
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
int vector; /* vector to which interrupt is connected */ int vector; /* vector to which interrupt is connected */
if (i->isr[0]) if (i->isr[0])
@ -173,7 +173,7 @@ static int initIRQ
irq_enable (1); irq_enable (1);
} }
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEXM */
#endif /* VXMICRO_ARCH_x86 */ #endif /* CONFIG_X86_32 */
return 0; return 0;
} }

2
include/arch/cpu.h
View file

@ -33,7 +33,7 @@
#ifndef __ARCHCPU_H__ #ifndef __ARCHCPU_H__
#define __ARCHCPU_H__ #define __ARCHCPU_H__
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
#include <arch/x86/arch.h> #include <arch/x86/arch.h>
#elif defined(VXMICRO_ARCH_arm) #elif defined(VXMICRO_ARCH_arm)
#include <arch/arm/arch.h> #include <arch/arm/arch.h>

4
include/linker-defs.h
View file

@ -45,7 +45,7 @@ This file may be included by:
#include <sections.h> #include <sections.h>
/* include platform dependent linker-defs */ /* include platform dependent linker-defs */
#ifdef VXMICRO_ARCH_x86 #ifdef CONFIG_X86_32
#include <arch/x86/linker-defs-arch.h> #include <arch/x86/linker-defs-arch.h>
#elif defined(VXMICRO_ARCH_arm) #elif defined(VXMICRO_ARCH_arm)
/* Nothing yet to include */ /* Nothing yet to include */
@ -56,7 +56,7 @@ This file may be included by:
#endif #endif
#ifdef _LINKER #ifdef _LINKER
#ifdef VXMICRO_ARCH_x86 /* LINKER FILES: defines used by linker script */ #ifdef CONFIG_X86_32 /* LINKER FILES: defines used by linker script */
/* Should be moved to linker-common-defs.h */ /* Should be moved to linker-common-defs.h */
#if defined(CONFIG_XIP) #if defined(CONFIG_XIP)
#define ROMABLE_REGION ROM #define ROMABLE_REGION ROM

2
include/sections.h
View file

@ -50,7 +50,7 @@
/* Various text section names */ /* Various text section names */
#define TEXT text #define TEXT text
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
#define TEXT_START text_start /* beginning of TEXT section */ #define TEXT_START text_start /* beginning of TEXT section */
#else #else
#define TEXT_START text /* beginning of TEXT section */ #define TEXT_START text /* beginning of TEXT section */

2
include/toolchain/common.h
View file

@ -85,7 +85,7 @@ Macros to abstract compiler capabilities (common to all toolchains).
#ifdef _ASMLANGUAGE #ifdef _ASMLANGUAGE
#ifdef VXMICRO_ARCH_x86 #ifdef CONFIG_X86_32
#ifdef PERF_OPT #ifdef PERF_OPT
#define PERFOPT_ALIGN .balign 16 #define PERFOPT_ALIGN .balign 16

2
include/toolchain/gcc.h
View file

@ -294,7 +294,7 @@ A##a:
",%B0" \ ",%B0" \
"\n\t.type\t" #name ",%%object" : : "n"(~(value))) "\n\t.type\t" #name ",%%object" : : "n"(~(value)))
#elif defined(VXMICRO_ARCH_x86) || defined(VXMICRO_ARCH_arc) #elif defined(CONFIG_X86_32) || defined(VXMICRO_ARCH_arc)
#define GEN_ABSOLUTE_SYM(name, value) \ #define GEN_ABSOLUTE_SYM(name, value) \
__asm__(".globl\t" #name "\n\t.equ\t" #name \ __asm__(".globl\t" #name "\n\t.equ\t" #name \

2
kernel/microkernel/k_irq.c
View file

@ -87,7 +87,7 @@ static struct task_irq_info task_irq_object[MAX_TASK_IRQS] = {
/* architecture-specific */ /* architecture-specific */
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
/* task IRQ interrupt stub array */ /* task IRQ interrupt stub array */
NANO_CPU_INT_STUB_DECL(irq_obj_mem_stub[MAX_TASK_IRQS]); NANO_CPU_INT_STUB_DECL(irq_obj_mem_stub[MAX_TASK_IRQS]);

2
kernel/nanokernel/nano_init.c
View file

@ -186,7 +186,7 @@ static void nano_init(tCCS *dummyOutContext)
extern void *__stack_chk_guard; extern void *__stack_chk_guard;
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
#define _MOVE_INSTR "movl " #define _MOVE_INSTR "movl "
#elif defined(VXMICRO_ARCH_arm) #elif defined(VXMICRO_ARCH_arm)
#define _MOVE_INSTR "str " #define _MOVE_INSTR "str "

10
samples/include/irq_test_common.h
View file

@ -39,7 +39,7 @@ Interrupt stuff, abstracted across CPU architectures.
#ifndef _IRQ_TEST_COMMON__H_ #ifndef _IRQ_TEST_COMMON__H_
#define _IRQ_TEST_COMMON__H_ #define _IRQ_TEST_COMMON__H_
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3 #define IRQ_PRIORITY 3
#elif defined(VXMICRO_ARCH_arm) #elif defined(VXMICRO_ARCH_arm)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEXM)
@ -57,7 +57,7 @@ Interrupt stuff, abstracted across CPU architectures.
#error NUM_SW_IRQS only supports 1 or 2 IRQs #error NUM_SW_IRQS only supports 1 or 2 IRQs
#endif #endif
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
static NANO_CPU_INT_STUB_DECL(nanoIntStub1); static NANO_CPU_INT_STUB_DECL(nanoIntStub1);
#if NUM_SW_IRQS >= 2 #if NUM_SW_IRQS >= 2
static NANO_CPU_INT_STUB_DECL(nanoIntStub2); static NANO_CPU_INT_STUB_DECL(nanoIntStub2);
@ -67,7 +67,7 @@ Interrupt stuff, abstracted across CPU architectures.
typedef void (*vvfn)(void); /* void-void function pointer */ typedef void (*vvfn)(void); /* void-void function pointer */
typedef void (*vvpfn)(void *); /* void-void_pointer function pointer */ typedef void (*vvpfn)(void *); /* void-void_pointer function pointer */
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
/* /*
* Opcode for generating a software interrupt. The ISR associated with each * Opcode for generating a software interrupt. The ISR associated with each
* of these software interrupts will call either nano_isr_lifo_put() or * of these software interrupts will call either nano_isr_lifo_put() or
@ -120,7 +120,7 @@ struct isrInitInfo {
static int initIRQ(struct isrInitInfo *i) static int initIRQ(struct isrInitInfo *i)
{ {
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
int vector; /* vector to which interrupt is connected */ int vector; /* vector to which interrupt is connected */
if (i->isr[0]) { if (i->isr[0]) {
@ -153,7 +153,7 @@ static int initIRQ(struct isrInitInfo *i)
irq_enable(1); irq_enable(1);
} }
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEXM */
#endif /* VXMICRO_ARCH_x86 */ #endif /* CONFIG_X86_32 */
return 0; return 0;
} }

2
samples/microkernel/benchmark/footprint/src/test_asm_inline_gcc.h
View file

@ -33,7 +33,7 @@
#ifndef _TEST_ASM_INLINE_GCC_H #ifndef _TEST_ASM_INLINE_GCC_H
#define _TEST_ASM_INLINE_GCC_H #define _TEST_ASM_INLINE_GCC_H
#if !defined(__GNUC__) || !defined(VXMICRO_ARCH_x86) #if !defined(__GNUC__) || !defined(CONFIG_X86_32)
#error test_asm_inline_gcc.h goes only with x86 GCC #error test_asm_inline_gcc.h goes only with x86 GCC
#endif #endif

2
samples/microkernel/benchmark/latency_measure/src/raise_int.c
View file

@ -40,7 +40,7 @@
#include <stdint.h> #include <stdint.h>
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
static void genInt0 (void) static void genInt0 (void)
{ {

2
samples/microkernel/benchmark/latency_measure/src/test_asm_inline_gcc.h
View file

@ -33,7 +33,7 @@
#ifndef _TEST_ASM_INLINE_GCC_H #ifndef _TEST_ASM_INLINE_GCC_H
#define _TEST_ASM_INLINE_GCC_H #define _TEST_ASM_INLINE_GCC_H
#if !defined(__GNUC__) || !defined(VXMICRO_ARCH_x86) #if !defined(__GNUC__) || !defined(CONFIG_X86_32)
#error test_asm_inline_gcc.h goes only with x86 GCC #error test_asm_inline_gcc.h goes only with x86 GCC
#endif #endif

2
samples/microkernel/test/test_static_idt/src/test_asm_inline_gcc.h
View file

@ -33,7 +33,7 @@
#ifndef _TEST_ASM_INLINE_GCC_H #ifndef _TEST_ASM_INLINE_GCC_H
#define _TEST_ASM_INLINE_GCC_H #define _TEST_ASM_INLINE_GCC_H
#if !defined(__GNUC__) || !defined(VXMICRO_ARCH_x86) #if !defined(__GNUC__) || !defined(CONFIG_X86_32)
#error test_asm_inline_gcc.h goes only with x86 GCC #error test_asm_inline_gcc.h goes only with x86 GCC
#endif #endif

2
samples/microkernel/test/test_task_irq/src/raise_int.c
View file

@ -40,7 +40,7 @@
#include <stdint.h> #include <stdint.h>
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
static void genInt0(void) static void genInt0(void)
{ {

2
samples/microkernel/test/test_task_irq/src/test_device.c
View file

@ -51,7 +51,7 @@ exercises the task_irq_free() API.
#define DEV4_ID 3 #define DEV4_ID 3
#define DEV5_ID 4 #define DEV5_ID 4
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
#define DEV1_IRQ 8 #define DEV1_IRQ 8
#define DEV2_IRQ 14 #define DEV2_IRQ 14
#define DEV3_IRQ 32 #define DEV3_IRQ 32

6
samples/microkernel/test/test_tickless/src/test_tickless.c
View file

@ -55,7 +55,7 @@ extern int32_t _sys_idle_threshold_ticks;
* timestamp routines. * timestamp routines.
*/ */
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
typedef uint64_t _timer_res_t; typedef uint64_t _timer_res_t;
#define _TIMER_ZERO 0ULL #define _TIMER_ZERO 0ULL
@ -133,7 +133,7 @@ void ticklessTestTask(void)
} }
cal_tsc /= CAL_REPS; cal_tsc /= CAL_REPS;
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
printk("Calibrated time stamp period = 0x%x%x\n", printk("Calibrated time stamp period = 0x%x%x\n",
(uint32_t)(cal_tsc >> 32), (uint32_t)(cal_tsc & 0xFFFFFFFFLL)); (uint32_t)(cal_tsc >> 32), (uint32_t)(cal_tsc & 0xFFFFFFFFLL));
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
@ -170,7 +170,7 @@ void ticklessTestTask(void)
printk("end ticks : %d\n", end_ticks); printk("end ticks : %d\n", end_ticks);
printk("diff ticks : %d\n", diff_ticks); printk("diff ticks : %d\n", diff_ticks);
#if defined(VXMICRO_ARCH_x86) #if defined(CONFIG_X86_32)
printk("diff time stamp: 0x%x%x\n", printk("diff time stamp: 0x%x%x\n",
(uint32_t)(diff_tsc >> 32), (uint32_t)(diff_tsc & 0xFFFFFFFFULL)); (uint32_t)(diff_tsc >> 32), (uint32_t)(diff_tsc & 0xFFFFFFFFULL));
printk("Cal time stamp: 0x%x%x\n", printk("Cal time stamp: 0x%x%x\n",

2
samples/nanokernel/benchmark/footprint/src/test_asm_inline_gcc.h
View file

@ -33,7 +33,7 @@
#ifndef _TEST_ASM_INLINE_GCC_H #ifndef _TEST_ASM_INLINE_GCC_H
#define _TEST_ASM_INLINE_GCC_H #define _TEST_ASM_INLINE_GCC_H
#if !defined(__GNUC__) || !defined(VXMICRO_ARCH_x86) #if !defined(__GNUC__) || !defined(CONFIG_X86_32)
#error test_asm_inline_gcc.h goes only with x86 GCC #error test_asm_inline_gcc.h goes only with x86 GCC
#endif #endif

3
scripts/Makefile.x86.preparch
View file

@ -10,7 +10,6 @@ ifneq ($(CONFIG_BSP_QUARK),y)
iSSE_FP_MATH_ ?= -mno-sse iSSE_FP_MATH_ ?= -mno-sse
iSSE_FP_MATH ?= ${iSSE_FP_MATH_${CONFIG_SSE_FP_MATH}} iSSE_FP_MATH ?= ${iSSE_FP_MATH_${CONFIG_SSE_FP_MATH}}
endif endif
x86_FLAGS = -DVXMICRO_ARCH_x86
x86_FLAGS += -DVXMICRO_ARCH=x86 x86_FLAGS += -DVXMICRO_ARCH=x86
x86_FLAGS += $(ALIGN_STACK_FLAG) x86_FLAGS += $(ALIGN_STACK_FLAG)
x86_FLAGS += $(SECTION_GC_FLAG) x86_FLAGS += $(SECTION_GC_FLAG)
@ -19,8 +18,6 @@ x86_FLAGS += $(LTO_FLAG)
x86_FLAGS += $(PERF_OPT_FLAG) x86_FLAGS += $(PERF_OPT_FLAG)
x86_FLAGS += $(iSSE_FP_MATH) x86_FLAGS += $(iSSE_FP_MATH)
LDFLAG_LINKERCMD = -DVXMICRO_ARCH_x86
ISA_FLAG_pentium4-$(CONFIG_BSP_PCPENTIUM4) = -march=pentium4 ISA_FLAG_pentium4-$(CONFIG_BSP_PCPENTIUM4) = -march=pentium4
ISA_FLAG_minuteia-$(CONFIG_BSP_PCMINUTEIA) = -march=pentium ISA_FLAG_minuteia-$(CONFIG_BSP_PCMINUTEIA) = -march=pentium
ISA_FLAG_atom_n28xx-$(CONFIG_BSP_ATOM_N28XX) = -march=atom -mtune=atom ISA_FLAG_atom_n28xx-$(CONFIG_BSP_ATOM_N28XX) = -march=atom -mtune=atom