From 1916fb21dd7528fabbef0b5cf35f684959463a5c Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 12 Apr 2022 16:54:58 -0500 Subject: [PATCH] drivers: pinctrl: update lpc pinctrl driver for lpc11u6x Update pin control driver for lpc11u6x. This SOC does not have a HAL, so fsl_clock is not available. It also lacks a slew-rate field in the IOCON register, so this property must be optional. Signed-off-by: Daniel DeGrasse --- drivers/pinctrl/Kconfig.lpc_iocon | 4 +- drivers/pinctrl/pinctrl_lpc_iocon.c | 10 +-- .../pinctrl/nxp,lpc-iocon-pinctrl.yaml | 9 +++ .../pinctrl/nxp,lpc11u6x-pinctrl.yaml | 66 +++++++++++++++++++ 4 files changed, 84 insertions(+), 5 deletions(-) create mode 100644 dts/bindings/pinctrl/nxp,lpc11u6x-pinctrl.yaml diff --git a/drivers/pinctrl/Kconfig.lpc_iocon b/drivers/pinctrl/Kconfig.lpc_iocon index 7a3c9452ed3..23c1f7c7c6b 100644 --- a/drivers/pinctrl/Kconfig.lpc_iocon +++ b/drivers/pinctrl/Kconfig.lpc_iocon @@ -2,12 +2,14 @@ # SPDX-License-Identifier: Apache-2.0 DT_COMPAT_NXP_LPC_PINCTRL := nxp,lpc-iocon-pinctrl +DT_COMPAT_NXP_LPC_11U6X_PINCTRL := nxp,lpc11u6x-pinctrl DT_COMPAT_NXP_RT_PINCTRL := nxp,rt-iocon-pinctrl config PINCTRL_NXP_IOCON bool "IOCON Pin controller driver for NXP LPC MCUs" depends on SOC_FAMILY_LPC || SOC_SERIES_IMX_RT6XX || SOC_SERIES_IMX_RT5XX default $(dt_compat_enabled,$(DT_COMPAT_NXP_LPC_PINCTRL)) || \ - $(dt_compat_enabled,$(DT_COMPAT_NXP_RT_PINCTRL)) + $(dt_compat_enabled,$(DT_COMPAT_NXP_RT_PINCTRL)) || \ + $(dt_compat_enabled,$(DT_COMPAT_NXP_LPC_11U6X_PINCTRL)) help Enable pin controller driver for NXP LPC MCUs diff --git a/drivers/pinctrl/pinctrl_lpc_iocon.c b/drivers/pinctrl/pinctrl_lpc_iocon.c index 9de630da90e..d1dd5895aa3 100644 --- a/drivers/pinctrl/pinctrl_lpc_iocon.c +++ b/drivers/pinctrl/pinctrl_lpc_iocon.c @@ -5,7 +5,9 @@ */ #include +#if !defined(CONFIG_SOC_SERIES_LPC11U6X) #include +#endif #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) #define TYPE(mux) (((mux) & 0xC0000) >> 18) @@ -37,7 +39,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, break; default: /* Should not occur */ - assert(TYPE(pin_mux <= IOCON_TYPE_A)); + __ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A); } /* Set pinmux */ *(iocon + offset) = pin_mux; @@ -45,8 +47,8 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, return 0; } -#ifdef CONFIG_SOC_FAMILY_LPC -/* LPC family needs iocon clock to be enabled */ +#if defined(CONFIG_SOC_FAMILY_LPC) && !defined(CONFIG_SOC_SERIES_LPC11U6X) +/* LPC family (except 11u6x) needs iocon clock to be enabled */ static int pinctrl_clock_init(const struct device *dev) { @@ -58,4 +60,4 @@ static int pinctrl_clock_init(const struct device *dev) SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); -#endif /* CONFIG_SOC_FAMILY_LPC */ +#endif /* CONFIG_SOC_FAMILY_LPC && !CONFIG_SOC_SERIES_LPC11U6X */ diff --git a/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml b/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml index 271c4e2801a..852fcfee4c3 100644 --- a/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml +++ b/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml @@ -40,6 +40,14 @@ description: | bias-pull-down: IOCON_MODE=1 drive-push-pull: IOCON_MODE=3 + Note: for the LPC11u6x, the following fields are also supported: + IOCON_HYS- set by input-schmitt-enable + IOCON_S_MODE- set by nxp,digital-filter + IOCON_CLKDIV- set by nxp,filter-clock-div + IOCON_FILTR- set by nxp,analog-filter + + + compatible: "nxp,lpc-iocon-pinctrl" include: @@ -52,6 +60,7 @@ include: - bias-pull-up - bias-pull-down - drive-push-pull + - input-schmitt-enable child-binding: description: LPC IOCON pin controller pin group diff --git a/dts/bindings/pinctrl/nxp,lpc11u6x-pinctrl.yaml b/dts/bindings/pinctrl/nxp,lpc11u6x-pinctrl.yaml new file mode 100644 index 00000000000..8a0732b8945 --- /dev/null +++ b/dts/bindings/pinctrl/nxp,lpc11u6x-pinctrl.yaml @@ -0,0 +1,66 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +compatible: "nxp,lpc11u6x-pinctrl" + +include: + - name: base.yaml + - name: nxp,lpc-iocon-pinctrl.yaml + child-binding: + child-binding: + property-allowlist: + - pinmux + - nxp,invert + - nxp,analog-mode + - nxp,i2c-mode + - nxp,i2c-filter + - name: pincfg-node-group.yaml + child-binding: + child-binding: + property-allowlist: + - drive-open-drain + - bias-pull-up + - bias-pull-down + - drive-push-pull + - input-schmitt-enable + +child-binding: + description: LPC IOCON pin controller pin group + child-binding: + description: | + LPC IOCON pin controller pin configuration node + properties: + nxp,digital-filter: + type: int + default: 0 + enum: + - 0 + - 1 + - 2 + - 3 + description: | + Enable digital filter. Set number of clock cycles to use as rejection + threshold for input pulses. 0 disables the filter. Only valid for + lpc11u6x SOC. Filter defaults to disabled, as this is default reset + value for SOC + nxp,filter-clock-div: + type: int + default: 0 + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + description: | + set peripheral clock divider for input filter sampling clock + IOCONCLKDIV. Only valid for lpc11u6x SOC. Default to 0, as this + is the default reset value for the SOC. + nxp,disable-analog-filter: + type: boolean + description: | + Disable fixed 10 ns input glitch analog filter. Only valid for lpc11u6x + SOC, on analog pins. Note that this filter is enabled on reset, hence + the choice to make disabling the filter opt-in