boards: microchip: add icicle kit smp variant

With the introduction of the new Hardware model, we now have an easy
method to describe variants of boards. This is especially helpful for
Microchip's PolarFire SoC Icicle Kit which has a heterogeneous
core-complex. Introduce an SMP capable variant with four SMP capable
harts for the SMP cluster and disables the e51 monitor hart

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>

boards/microchip/mpfs_icicle/board.yml

@@ -3,3 +3,5 @@ board:
   vendor: microchip
   socs:
   - name: polarfire
+    variants:
+    - name: 'smp'

boards/microchip/mpfs_icicle/doc/index.rst

@@ -23,6 +23,11 @@ Applications for the ``mpfs_icicle`` board configuration can be built as usual
    :board: mpfs_icicle
    :goals: build
 
+To build the default SMP capable variant
+
+.. zephyr-app-commands::
+   :board: mpfs_icicle/polarfire/smp
+   :goals: build
 
 Flashing
 ========

boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020-2021 Microchip Technology Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <microchip/mpfs.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+
+/ {
+	model = "Microchip PolarFire-SoC Icicle Kit";
+	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		sw0 = &sw0;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+	};
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led0 {
+			gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
+			label = "LED_0";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		sw0: sw0 {
+			gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+			label = "SW_0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};
+
+&qspi0 {
+	status = "okay";
+	qspi_flash: spi-nor-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		size = <DT_SIZE_M(256)>;
+		jedec-id = [20 ba 19];
+	};
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&syscontroller_qspi {
+	status = "okay";
+	sys_ctrl_flash: spi-nor-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};

boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml

@@ -0,0 +1,12 @@
+identifier: mpfs_icicle/polarfire/smp
+name: Microchip PolarFire ICICLE kit (SMP)
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+ram: 3840
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: microchip

boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig

@@ -0,0 +1,14 @@
+CONFIG_MPFS_HAL=n
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_GPIO=y
+CONFIG_I2C=y
+CONFIG_SMP=y
+CONFIG_RV_BOOT_HART=1
+CONFIG_MP_MAX_NUM_CPUS=4