diff --git a/soc/arm/nordic_nrf/nrf51/CMakeLists.txt b/soc/arm/nordic_nrf/nrf51/CMakeLists.txt
index 82548794e61..bdbeda41ac9 100644
--- a/soc/arm/nordic_nrf/nrf51/CMakeLists.txt
+++ b/soc/arm/nordic_nrf/nrf51/CMakeLists.txt
@@ -5,5 +5,6 @@ zephyr_compile_definitions_ifdef(
   )
 
 zephyr_sources(
+  power.c
   soc.c
   )
diff --git a/soc/arm/nordic_nrf/nrf51/power.c b/soc/arm/nordic_nrf/nrf51/power.c
new file mode 100644
index 00000000000..2e90d68dd38
--- /dev/null
+++ b/soc/arm/nordic_nrf/nrf51/power.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr.h>
+#include <nrf_power.h>
+
+/* Overrides the weak ARM implementation:
+   Set general purpose retention register and reboot */
+void sys_arch_reboot(int type)
+{
+	nrf_power_gpregret_set((uint8_t)type);
+	NVIC_SystemReset();
+}
diff --git a/soc/arm/nordic_nrf/nrf52/power.c b/soc/arm/nordic_nrf/nrf52/power.c
index d8641c4bf5e..9ee8ac23984 100644
--- a/soc/arm/nordic_nrf/nrf52/power.c
+++ b/soc/arm/nordic_nrf/nrf52/power.c
@@ -115,3 +115,11 @@ bool _sys_soc_is_valid_power_state(enum power_states state)
 
 	return false;
 }
+
+/* Overrides the weak ARM implementation:
+   Set general purpose retention register and reboot */
+void sys_arch_reboot(int type)
+{
+	nrf_power_gpregret_set((uint8_t)type);
+	NVIC_SystemReset();
+}