diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index faa3f876bae..612ae6198f1 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -176,29 +176,8 @@ /* HP SRAM windows */ -/* window 3 */ -#define SRAM_TRACE_BASE 0xbe000000 -#define SRAM_TRACE_SIZE 0x2000 - -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE - -/* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) -#define SRAM_DEBUG_SIZE 0x800 - -#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) -#define SRAM_EXCEPT_SIZE 0x800 - -#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) -#define SRAM_STREAM_SIZE 0x1000 - -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - /* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) #define SRAM_SW_REG_SIZE 0x1000 #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) @@ -207,6 +186,26 @@ #define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 + +/* window 2 */ +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +/* window 3 */ +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x2000 + +#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE +#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE #define SOF_TEXT_START 0xbe010400 diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 0f96fa22922..7a35852a6b3 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -176,29 +176,9 @@ /* HP SRAM windows */ -/* window 3 */ -#define SRAM_TRACE_BASE 0xbe000000 -#define SRAM_TRACE_SIZE 0x2000 - -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE - -/* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) -#define SRAM_DEBUG_SIZE 0x800 - -#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) -#define SRAM_EXCEPT_SIZE 0x800 - -#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) -#define SRAM_STREAM_SIZE 0x1000 - -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - +/* HP SRAM windows */ /* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) #define SRAM_SW_REG_SIZE 0x1000 #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) @@ -207,6 +187,30 @@ #define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 + +/* window 2 */ +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +/* window 3 */ +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#if CONFIG_TRACE +#define SRAM_TRACE_SIZE 0x2000 +#else +#define SRAM_TRACE_SIZE 0x0 +#endif + +#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE +#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE #define SOF_TEXT_START 0xbe010400 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 35dd0fbdfc8..cd365bf539f 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -176,29 +176,8 @@ /* HP SRAM windows */ -/* window 3 */ -#define SRAM_TRACE_BASE 0xbe000000 -#define SRAM_TRACE_SIZE 0x2000 - -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE - -/* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) -#define SRAM_DEBUG_SIZE 0x800 - -#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) -#define SRAM_EXCEPT_SIZE 0x800 - -#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) -#define SRAM_STREAM_SIZE 0x1000 - -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - /* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) #define SRAM_SW_REG_SIZE 0x1000 #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) @@ -207,6 +186,30 @@ #define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 + +/* window 2 */ +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +/* window 3 */ +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#if CONFIG_TRACE +#define SRAM_TRACE_SIZE 0x2000 +#else +#define SRAM_TRACE_SIZE 0x0 +#endif + +#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE +#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE #define SOF_TEXT_START 0xbe010400